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ADSP-TS201S_06

更新时间： 2024-11-05 04:48:55
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亚德诺 - ADI /
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48页 1656K
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TigerSHARC-R Embedded Processor

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•
TigerSHARC®  
Embedded Processor  
a
ADSP-TS201S  
KEY FEATURES  
KEY BENEFITS  
Up to 600 MHz, 1.67 ns instruction cycle rate  
24M bits of internal—on-chip—DRAM memory  
25 mm × 25 mm (576-ball) thermally enhanced ball grid  
array package  
Dual-computation blocks—each containing an ALU, a  
multiplier, a shifter, a register file, and a communications  
logic unit (CLU)  
Dual-integer ALUs, providing data addressing and pointer  
manipulation  
Integrated I/O includes 14-channel DMA controller, external  
port, four link ports, SDRAM controller, programmable  
flag pins, two timers, and timer expired pin for system  
integration  
Provides high performance static superscalar DSP  
operations, optimized for telecommunications  
infrastructure and other large, demanding multiprocessor  
DSP applications  
Performs exceptionally well on DSP algorithm and I/O  
benchmarks (see benchmarks in Table 1)  
Supports low overhead DMA transfers between internal  
memory, external memory, memory-mapped peripherals,  
link ports, host processors, and other  
(multiprocessor) DSPs  
Eases DSP programming through extremely flexible instruc-  
tion set and high-level-language-friendly DSP architecture  
Enables scalable multiprocessing systems with low commu-  
nications overhead  
1149.1 IEEE-compliant JTAG test access port for on-chip  
emulation  
Provides on-chip arbitration for glueless multiprocessing  
Single-precision IEEE 32-bit and extended-precision 40-bit  
floating-point data formats and 8-, 16-, 32-, and 64-bit  
fixed-point data formats  
JTAG PORT  
6
DATA ADDRESS GENERATION  
24M BITS INTERNAL MEMORY  
SOC BUS  
32  
32  
MEMORY BLOCKS  
(PAGE CACHE)  
INTEGER  
J ALU  
INTEGER  
K ALU  
JTAG  
EXTERNAL  
PORT  
32-BIT × 32-BIT  
32-BIT × 32-BIT  
4 × CROSSBAR CONNECT  
PROGRAM  
SEQUENCER  
32  
A
A
A
A
D
D
D
D
ADDR  
HOST  
32  
128  
32  
J-BUS ADDR  
ADDR  
FETCH  
64  
8
MULTI-  
PROC  
DATA  
CTRL  
CTRL  
J-BUS DATA  
K-BUS ADDR  
K-BUS DATA  
I-BUS ADDR  
I-BUS DATA  
SDRAM  
CTRL  
10  
BTB  
C-BUS  
ARB  
128  
32  
SOC  
I/F  
EXT DMA  
REQ  
4
128  
DMA  
PC  
LINK PORTS  
4
21  
S-BUS ADDR  
S-BUS DATA  
8
4
8
4
IN  
L0  
L1  
L2  
L3  
128  
OUT  
IAB  
T
8
4
8
4
IN  
OUT  
8
4
8
4
IN  
128  
128  
128  
OUT  
X
Y
8
4
8
IN  
REGISTER  
FILE  
REGISTER  
FILE  
32-BIT × 32-BIT  
128  
SHIFT ALU MUL  
MUL ALU SHIFT  
CLU  
CLU  
DAB DAB  
OUT  
32-BIT × 32-BIT  
COMPUTATIONAL BLOCKS  
Figure 1. Functional Block Diagram  
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
1234567...48

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