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ADSP-TS101SAB2-000

更新时间： 2024-11-06 04:48:55
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
44页 828K
描述
Embedded Processor

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ADSP-TS101SAB2-000 数据手册

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T
a
Embedded Processor  
ADSP-TS101S  
KEY FEATURES  
KEY BENEFITS  
300 MHz, 3.3 ns Instruction Cycle Rate  
6M Bits of Internal—On-Chip—SRAM Memory  
19 mm 
؋
 19 mm (484-Ball) or 27 mm 
؋
 27 mm  
(625-Ball) PBGA Package  
Provides High Performance Static Superscalar DSP  
Operations, Optimized for Telecommunications  
Infrastructure and Other Large, Demanding  
Multiprocessor DSP Applications  
Dual Computation Blocks—Each Containing an ALU, a  
Multiplier, a Shifter, and a Register File  
Dual Integer ALUs, Providing Data Addressing and  
Pointer Manipulation  
Integrated I/O Includes 14 Channel DMA Controller,  
External Port, Four Link Ports, SDRAM Controller,  
Programmable Flag Pins, Two Timers, and Timer  
Expired Pin for System Integration  
1149.1 IEEE Compliant JTAG Test Access Port for  
On-Chip Emulation  
On-Chip Arbitration for Glueless Multiprocessing with  
up to Eight TigerSHARC Processors on a Bus  
Performs Exceptionally Well on DSP Algorithm and I/O  
Benchmarks (See Benchmarks in Table 1 and Table 2)  
Supports Low Overhead DMA Transfers Between  
Internal Memory, External Memory, Memory-Mapped  
Peripherals, Link Ports, Host Processors, and Other  
(Multiprocessor) DSPs  
Eases DSP Programming Through Extremely Flexible  
Instruction Set and High Level Language Friendly DSP  
Architecture  
Enables Scalable Multiprocessing Systems with Low  
Communications Overhead  
FUNCTIONAL BLOCK DIAGRAM  
COMPUTATIONAL BLOCKS  
SHIFTER  
PROGRAM SEQUENCER  
PC BTB IRQ  
DATA ADDRESS GENERATION  
INTERNAL MEMORY  
6
JTAG PORT  
MEMORY MEMORY MEMORY  
32  
32  
INTEGER  
J ALU  
INTEGER  
K ALU  
M0  
M1  
M2  
64Kx32  
64Kx32  
64Kx32  
ADDR  
SDRAM CONTROLLER  
32x32  
32x32  
IAB  
FETCH  
A
D
A
D
A
D
ALU  
MULTIPLIER  
EXTERNAL PORT  
32  
M0 ADDR  
M0 DATA  
X
MULTIPROCESSOR  
INTERFACE  
128  
REGISTER  
FILE  
32  
32x32  
HOST INTERFACE  
INPUT FIFO  
32  
ADDR  
64  
M1 ADDR  
M1 DATA  
128 128  
DAB  
128  
DATA  
OUTPUT BUFFER  
OUTPUT FIFO  
32  
DAB  
M2 ADDR  
M2 DATA  
128  
CNTRL  
128 128  
CLUSTER BUS  
ARBITER  
I/O ADDRESS  
32  
Y
I/O PROCESSOR  
REGISTER  
FILE  
32x32  
3
8
3
8
L0  
DMA  
CONTROLLER  
LINK PORT  
CONTROLLER  
MULTIPLIER  
ALU  
L1  
L2  
L3  
DMA ADDRESS  
DMA DATA  
LINK  
PORTS  
32 256  
256  
3
8
LINK DATA  
CONTROL/  
STATUS/  
TCBs  
CONTROL/  
STATUS/  
BUFFERS  
3
8
SHIFTER  
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties that  
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
Tel:781/329-4700  
Fax:781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  
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ADSP-TS101SAB2Z000 ADI

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ADSP-TS101SAB2Z-000 ADI

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ADSP-TS101SAB2Z100 ADI

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ADSP-TS101SAB2Z-100 ADI

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ADSP-TS101SKB1250X ADI

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 		IC 64-BIT, 125 MHz, OTHER DSP, PBGA625, 27 X 27 MM, METRIC, PLASTIC, BGA-625, Digital Sign
ADSP-TS101SKB2250X ADI

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 		IC 64-BIT, 125 MHz, OTHER DSP, PBGA484, 19 X 19 MM, METRIC, PLASTIC, BGA-484, Digital Sign
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ADSP-TS201S_06 ADI

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