Datasheet > ADSP-SC589-ENG

ADSP-SC589-ENG

更新时间： 2024-11-06 00:53:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
168页	3426K
描述
SHARC plus Dual Core DSP with ARM Cortex-A5

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数据手册

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ADSP-SC589-ENG 数据手册

SHARC+ Dual Core

DSP with ARM Cortex-A5

Preliminary Technical Data

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant

Low system power across automotive temperature range

SYSTEM FEATURES

Dual enhanced SHARC+ high performance floating-point

cores

MEMORY

Up to 450 MHz per SHARC+ core

Up to 5 Mbits (640 kB) L1SRAM memory per core with

parity (optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed point

Large on-chip L2 SRAM with ECC protection, up to 256 kB

On-chip L2 ROM (512 kB)

Two L3 interfaces optimized for low system power, providing

16-bit interface to DDR3, DDR2 or LPDDR1 SDRAM devices

ADDITIONAL FEATURES

Byte, short-word, word, long-word addressed

ARM Cortex-A5 core

Security and Protection

Crypto hardware accelerators

Fast secure boot with IP protection

Support for TrustZone^®

450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle

32 kB L1 instruction cache/32 kB L1 data cache

256 kB L2 cache with parity

Accelerators

Powerful DMA system

High performance pipelined FFT/IFFT engine

FIR, IIR, HAE, SINC offload engines

On-chip memory protection

Integrated safety features

PERIPHERALS

SYSTEM CONTROL

SRU

SECURITY AND PROTECTION

4× PRECISION CLOCK

CORE 0

CORE 1

CORE 2

SYSTEM PROTECTION (SPU)

GENERATORS

2x DAI

2x PIN

BUFFER

ASRC

8× PAIRS

FULL SPORT

0-7

SYSTEM MEMORY

PROTECTION UNIT (SMPU)

FAULT MANAGEMENT

2× S/PDIF Rx/Tx

ARM TrustZone SECURITY

3× I²C

L1 CACHE

32 kB L1 I-CACHE

32 kB L1 D-CACHE

DUAL CRC

2× LINK PORTS

L1 SRAM (PARITY)

WATCHDOGS

2× SPI + 1× QUAD SPI

5M BITS (640 kB)

SRAM/CACHE

5M BITS (640 kB)

SRAM/CACHE

OTP MEMORY

L2 CACHE

256 kB (PARITY)

3× UARTs

1× EPPI

THERMAL SENSOR

PROGRAM FLOW

3× ePWM

SYS EVENT CONTROLLER (SEC)

8× TIMERS + 1× COUNTER

TRIGGER ROUTING (TRU)

ADC CONTROL MODULE

(ACM)

SYSTEM CROSSBAR AND DMA SUBSYSTEM

CLOCK, RESET, AND POWER

CLOCK GENERATION (CGU)

ASYNC MEMORY (16-BIT)

2× CAN2.0

CLOCK DISTRIBUTION

UNIT (CDU)

SD/SDIO/eMMC

L3 MEMORY

INTERFACES

SYSTEM

REAL TIME CLOCK (RTC)

RESET CONTROL (RCU)

MLB 3-PIN

2× EMAC

L2 MEMORY

ACCELERATION

2M BITS (256 kB)

L2 SRAM (ECC)

DSP FUNCTIONS

DDR3

DDR2

DDR3

DDR2

(FFT/iFFT, FIR, IIR, HAE/SINC)

SINC FILTER

POWER MANAGEMENT (DPM)

LPDDR1

4M BITS (512 kB)

2 × 2M BITS ROM

ENCRYPTION/DECRYPTION

8x SHARC FLAGS

DEBUG UNIT

2× USB 2.0 HS

MLB 6-PIN

ARM CoreSight

DATA

WATCHPOINTS (SWU)

PCIe2.0 (1 lane)

HADC (8 CHAN, 12-BIT)

Figure 1. Processor Block Diagram

Rev. PrF

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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与ADSP-SC589-ENG相关器件

型号	品牌	获取价格	描述	数据表
ADSP-SC591	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC592	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC592KBPZ10	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC592WCBPZ10	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC594	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC594-BPZENG	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC594KBPZ10	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC594KBPZ8	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC594WCBPZ10	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5
ADSP-SC594WCBPZ8	ADI	获取价格	SHARC Dual-Core DSP with Arm Cortex-A5

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