ADCLK950

更新时间： 2024-02-22 03:13:02

品牌	Logo	应用领域
亚德诺 - ADI		半导体时钟
页数	文件大小	规格书
12页	368K
描述
Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer

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技术参数
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ADCLK950 技术参数

生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	40
Reach Compliance Code：	unknown	风险等级：	5.76
系列：	950	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-XQCC-N40	长度：	6 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	40
实输出次数：	10	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	传播延迟（tpd）：	0.21 ns
认证状态：	COMMERCIAL	Same Edge Skew-Max（tskwd）：	0.045 ns
座面最大高度：	1 mm	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	2.97 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	INDUSTRIAL	端子面层：	NOT SPECIFIED
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	6 mm
Base Number Matches：	1

ADCLK950 数据手册

ADCLK950

return path. If the inputs are dc-coupled to a source, take care to

ensure that the pins are within the rated input differential and

common-mode ranges.

CLOCK INPUT SELECT (IN_SEL) SETTINGS

A Logic 0 on the IN_SEL pin selects the Input CLK0 and

Input

. A Logic 1 on the IN_SEL pin selects Input CLK1

CLK0

If the return is floated, the device exhibits a 100 ꢁ cross termi-

nation, but the source must then control the common-mode

voltage and supply the input bias currents.

and Input

CLK1

PCB LAYOUT CONSIDERATIONS

The ADCLK950 buffer is designed for very high speed applica-

tions. Consequently, high speed design techniques must be used

to achieve the specified performance. It is critically important

to use low impedance supply planes for both the negative supply

(V_EE) and the positive supply (V_CC) planes as part of a multilayer

board. Providing the lowest inductance return path for switching

currents ensures the best possible performance in the target

application.

There are ESD/clamp diodes between the input pins to prevent

the application from developing excessive offsets to the input

transistors. ESD diodes are not optimized for best ac perfor-

mance. When a clamp is required, it is recommended that

appropriate external diodes be used.

Exposed Metal Paddle

The exposed metal paddle on the ADCLK950 package is both

an electrical connection and a thermal enhancement. For the

device to function properly, the paddle must be properly

attached to the V_EEpower plane.

The following references to the GND plane assume that the V_EE

power plane is grounded for LVPECL operation. Note that for

ECL operation, the V_CCpower plane becomes the ground plane.

When properly mounted, the ADCLK950 also dissipates heat

through its exposed paddle. The PCB acts as a heat sink for the

ADCLK950. The PCB attachment must provide a good thermal

path to a larger heat dissipation area. This requires a grid of vias

from the top layer down to the V_EEpower plane (see Figure 18).

The ADCLK950 evaluation board (ADCLK950/PCBZ) pro-

vides an example of how to attach the part to the PCB.

It is also important to adequately bypass the input and output

supplies. Place a 1 μF electrolytic bypass capacitor within several

inches of each V_CCpower supply pin to the GND plane. In

addition, place multiple high quality 0.001 μF bypass capacitors

as close as possible to each of the V_CCsupply pins, and connect

the capacitors to the GND plane with redundant vias. Carefully

select high frequency bypass capacitors for minimum induc-

tance and ESR. To improve the effectiveness of the bypass at

high frequencies, minimize parasitic layout inductance. Also,

avoid discontinuities along input and output transmission lines

that can affect jitter performance.

VIAS TO V POWER

In a 50 Ω environment, input and output matching have a

significant impact on performance. The buffer provides internal

PLANE

CLKx

50 Ω termination resistors for both CLKx and

inputs.

Normally, the return side is connected to the reference pin that is

provided. Carefully bypass the termination potential using

ceramic capacitors to prevent undesired aberrations on the

input signal due to parasitic inductance in the termination

Figure 18. PCB Land for Attaching Exposed Paddle

Rev. 0 | Page 10 of 12

1...7 8 91011 12

中文翻译

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ADCLK950/PCBZ	ADI	Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK950BCPZ	ADI	Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK950BCPZ-REEL7	ADI	Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
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ADCLK954BCPZ	ADI	Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK954BCPZ-REEL7	ADI	Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
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ADCMP341_15	ADI	Comparators and Reference with Programmable Hysteresis	获取价格
ADCMP341ARJ	ADI	Dual Comparators with 400mV Reference and programmable Hysteresis	获取价格
ADCMP341YRJZ-REEL7	ADI	Dual 0.275% Comparators and Reference with Programmable Hysteresis	获取价格
ADCMP343	ADI	Dual Comparators with 400mV Reference and programmable Hysteresis	获取价格
ADCMP343_15	ADI	Comparators and Reference with Programmable Hysteresis	获取价格
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