ADCLK854

更新时间： 2024-02-02 07:51:15

品牌	Logo	应用领域
亚德诺 - ADI		时钟
页数	文件大小	规格书
16页	532K
描述
1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer

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ADCLK854 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	48
Reach Compliance Code：	unknown	风险等级：	5.75
Is Samacsys：	N	放大器类型：	BUFFER
最大平均偏置电流 (IIB)：	350 µA	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	NOT APPLICABLE	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	座面最大高度：	1 mm
子类别：	Buffer Amplifier	供电电压上限：	2 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	Base Number Matches：	1

ADCLK854 数据手册

1.8 V, 12-LVDS/24-CMOS Output,

Low Power Clock Fanout Buffer

ADCLK854

FEATURES

FUNCTIONAL BLOCK DIAGRAM

2 selectable differential inputs

Selectable LVDS/CMOS outputs

Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs

<12 mW per channel (100 MHz operation)

54 fs rms integrated jitter (12 kHz to 20 MHz)

100 fs rms additive broadband jitter

2.0 ns propagation delay (LVDS)

135 ps output rise/fall (LVDS)

ADCLK854

LVDS/

CMOS

V /2

OUT0 (OUT0A)

OUT0 (OUT0B)

REF

CLK0

OUT1 (OUT1A)

OUT1 (OUT1B)

CLK1

OUT2 (OUT2A)

OUT2 (OUT2B)

70 ps output-to-output skew (LVDS)

Sleep mode

Pin programmable control

IN_SEL

OUT3 (OUT3A)

OUT3 (OUT3B)

CTRL_A

1.8 V power supply

LVDS/

CMOS

OUT4 (OUT4A)

OUT4 (OUT4B)

APPLICATIONS

Low jitter clock distribution

Clock and data signal restoration

Level translation

Wireless communications

Wired communications

OUT5 (OUT5A)

OUT5 (OUT5B)

CTRL_B

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

Medical and industrial imaging

ATE and high performance instrumentation

GENERAL DESCRIPTION

LVDS/

CMOS

OUT8 (OUT8A)

OUT8 (OUT8B)

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout

buffer optimized for low jitter and low power operation. Possible

configurations range from 12 LVDS to 24 CMOS outputs,

including combinations of LVDS and CMOS outputs. Three

control lines are used to determine whether fixed blocks of

outputs (three banks of four) are LVDS or CMOS outputs.

OUT9 (OUT9A)

OUT9 (OUT9B)

CTRL_C

SLEEP

OUT10 (OUT10A)

OUT10 (OUT10B)

OUT11 (OUT11A)

OUT11 (OUT11B)

The ADCLK854 offers two selectable inputs and a sleep mode

feature. The IN_SEL pin state determines which input is fanned

out to all the outputs. The SLEEP pin enables a sleep mode to

power down the device.

Figure 1.

The inputs accept various types of single-ended and differential

logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.

Table 8 provides interface options for each type of connection.

This device is available in a 48-pin LFCSP package. It is specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks are theproperty of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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