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ADC1412D080 PDF预览

ADC1412D080

更新时间: 2024-11-05 06:36:19
品牌 Logo 应用领域
恩智浦 - NXP 双倍数据速率
页数 文件大小 规格书
37页 286K
描述
Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

ADC1412D080 数据手册

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ADC1412D065/080/105/125  
Dual 14-bit ADC 65, 80, 105 or 125 Msps  
CMOS or LVDS DDR digital outputs  
Rev. 02 — 4 June 2009  
Objective data sheet  
1. General description  
The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for  
high dynamic performances and low power consumption at sample rates up to 125 Msps.  
Pipelined architecture and output error correction ensure the ADC1412D is accurate  
enough to guarantee zero missing codes over the entire operating range. Supplied from a  
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,  
thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential  
Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral  
Interface) allows the user to easily configure the ADC. The device also includes a  
programmable gain amplifier with a flexible input voltage range. With excellent dynamic  
performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D  
is ideal for use in communications, imaging and medical applications.  
005aaa042  
0
005aaa040  
005aaa041  
1.5  
1
1.5  
dB  
1
0.5  
0
-40  
0.5  
0
-80  
-0.5  
-1  
-0.5  
-1  
-120  
-1.5  
-1.5  
0
10  
20  
30  
40  
0
4000  
8000  
12000  
16000  
0
4000  
8000  
12000  
16000  
f (MHz)  
Fig 1. Integral Non-Linearity (INL) Fig 2. Differential Non-Linearity  
(DNL)  
Fig 3. Output spectrum: 1 dBFS,  
80 Msps, fi = 4.43 MHz  
2. Features  
I SNR, 73 dB  
I Input bandwidth, 650 MHz  
I SFDR, 90 dBc  
I Power dissipation, 775 mW at 80 Msps  
I SPI Interface  
I Sample rate up to 125 Msps  
I Dual-channel14-bit pipelined ADC core I Duty cycle stabilizer  
I Single 3 V supply I Fast OTR detection  
I Flexible input voltage range: 1 V to 2 V I Offset binary, 2’s complement, gray  
(p-p) with 6 dB programmable fine gain  
I CMOS or LVDS DDR digital outputs  
I INL ±1 LSB, DNL ±0.5 LSB (typical)  
code  
I Power-down and Sleep modes  
I HVQFN64 package  

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