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ADC1412D125HN/C1,5

更新时间： 2024-09-26 14:49:11
品牌 Logo 应用领域
艾迪悌 - IDT 转换器
页数 文件大小 规格书
41页 582K
描述
IC IC,A/D CONVERTER,DUAL,14-BIT,LLCC,64PIN, Analog to Digital Converter

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ADC1412D125HN/C1,5 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：QCCN, LCC64,.35SQ,20
Reach Compliance Code：compliantECCN代码：3A991.C.3
HTS代码：8542.39.00.01风险等级：5.83
最大模拟输入电压：2 V转换器类型：A/D CONVERTER
JESD-30 代码：S-PQCC-N64JESD-609代码：e3
最大线性误差 (EL)：0.03%湿度敏感等级：1
位数：14功能数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC64,.35SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3 V认证状态：Not Qualified
子类别：Analog to Digital Converters标称供电电压：3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

ADC1412D125HN/C1,5 数据手册

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ADC1412D series  
Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;  
CMOS or LVDS DDR digital outputs  
Rev. 05 — 2 July 2012  
Product data sheet  
1. General description  
The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for  
high dynamic performance and low power consumption at sample rates up to 125 Msps.  
Pipelined architecture and output error correction ensure the ADC1412D is accurate  
enough to guarantee zero missing codes over the entire operating range. Supplied from a  
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in Complementary  
Metal Oxide Semiconductor (CMOS) mode because of a separate digital output supply. It  
supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output  
standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily  
configure the ADC. The device also includes an programmable full-scale SPI to allow a  
flexible input voltage range of 1 V (p-p) to 2 V (p-p). With excellent dynamic performance  
from the baseband to input frequencies of 170 MHz or more, the ADC1412D is ideal for  
use in communications, imaging and medical applications.  
2. Features and benefits  
SNR, 72.1 dBFS  
Input bandwidth, 600 MHz  
SFDR, 86 dBc  
Power dissipation, 855 mW at 80 Msps  
Serial Peripheral Interface (SPI)  
Sample rate up to 125 Msps  
Clock input divided by 2 to reduce jitter Duty cycle stabilizer  
contribution  
Single 3 V supply  
Fast OuT-of-Range (OTR) detection  
Flexible input voltage range:  
Offset binary, two’s complement, gray  
1 V to 2 V (p-p)  
code  
CMOS or LVDS DDR digital outputs  
Power-down and Sleep modes  
HVQFN64 package  
Pin and software compatible with  
ADC1212D series and ADC1112D125  
3. Applications  
Wireless and wired broadband  
Portable instrumentation  
communications  
Spectral analysis  
Imaging systems  
Ultrasound equipment  
Software defined radio  
®
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