Datasheet > ADC12DS105

ADC12DS105

更新时间： 2024-09-10 04:48:51

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器
页数	文件大小	规格书
30页	585K
描述
Dual 12-Bit, 65/80/95/105 MSPS A/D Converter with Serial LVDS outputs

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ADC12DS105 数据手册

ADVANCE INFORMATION

February 2007

ADC12DS065/ADC12DS080/ADC12DS095/ADC12DS105

Dual 12-Bit, 65/80/95/105 MSPS A/D Converter with Serial

LVDS outputs

General Description

Features

NOTE: This is Advance Information for products current-

ly in development. ALL specifications are design targets

and are subject to change.

1 GHz Full Power Bandwidth

■

Internal sample-and-hold circuit and precision reference

Low power consumption

The ADC12DS065, ADC12DS080, ADC12DS095, and AD-

C12DS105 are high-performance CMOS analog-to-digital

converters capable of converting two analog input signals into

12-bit digital words at rates up to 65/80/95/105 Mega Samples

Per Second (MSPS) respectively. The digital outputs are se-

rialized and provided on differential LVDS signal pairs. These

converters use a differential, pipelined architecture with digital

error correction and an on-chip sample-and-hold circuit to

minimize power consumption and the external component

count, while providing excellent dynamic performance. A

unique sample-and-hold stage yields a full-power bandwidth

of 1 GHz. The ADC12DS065/080/095/105 may be operated

from a single +3.3V power supply and consumes low power.

A power-down feature reduces the power consumption to

very low levels while still allowing fast wake-up time to full

operation. The differential inputs provide a 2V full scale dif-

ferential input swing. A stable 1.2V internal voltage reference

is provided, or the ADC12DS065/080/095/105 can be oper-

ated with an external 1.2V reference. Output data format

(offset binary versus 2's complement) and duty cycle stabi-

lizer are pin-selectable. The duty cycle stabilizer maintains

performance over a wide range of clock duty cycles.

Clock Duty Cycle Stabilizer

Single +3.3V supply operation

Offset binary or 2's complement output data format

Serial LVDS Outputs

60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)

Key Specifications

For ADC12DS105

Resolution

Conversion Rate

SNR (f_IN= 240 MHz)

SFDR (f_IN= 240 MHz)

Full Power Bandwidth

Power Consumption

■

12 Bits

105 MSPS

67 dBFS (typ)

83 dBFS (typ)

1 GHz (typ)

■

1060 mW (typ)

Applications

High IF Sampling Receivers

■

Wireless Base Station Receivers

Test and Measurement Equipment

The ADC12DS065/080/095/105 is available in a 60-lead LLP

package and operates over the industrial temperature range

of −40°C to +85°C.

Communications Instrumentation

Portable Instrumentation

■

Connection Diagram

20211701

202117

www.national.com

12 3 4 5 6 7...30

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与ADC12DS105相关器件

型号	品牌	获取价格	描述	数据表
ADC12DS105_08	NSC	获取价格	Dual 12-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs
ADC12DS105CISQ	NSC	获取价格	Dual 12-Bit, 65/80/95/105 MSPS A/D Converter with Serial LVDS outputs
ADC12DS105CISQ/NOPB	TI	获取价格	双通道、12 位、105MSPS 模数转换器 (ADC) \| NKA \| 60 \| -40
ADC12DS105CISQE/NOPB	TI	获取价格	双通道、12 位、105MSPS 模数转换器 (ADC) \| NKA \| 60 \| -40
ADC12DS105LFEB	NSC	获取价格	Dual 12-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs
ADC12EU050	NSC	获取价格	Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Analog-to-Digital Converter
ADC12EU050_0811	NSC	获取价格	Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta Analog-to-Digital Converter
ADC12EU050_09	NSC	获取价格	Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta Analog-to-Digital Converter
ADC12EU050CILQ	NSC	获取价格	Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Analog-to-Digital Converter
ADC12EU050CIPLQ	NSC	获取价格	Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta Analog-to-Digital Converter

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