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ADC12DS105CISQ/NOPB PDF预览

ADC12DS105CISQ/NOPB

更新时间： 2024-09-11 11:13:39
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德州仪器 - TI 转换器模数转换器
页数 文件大小 规格书
35页 692K
描述
双通道、12 位、105MSPS 模数转换器 (ADC) | NKA | 60 | -40 to 85

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ADC12DS105CISQ/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC60,.35SQ,20针数：60
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.21最大模拟输入电压：1.6 V
最小模拟输入电压：1.4 V最长转换时间：0.152 µs
转换器类型：ADC, PROPRIETARY METHODJESD-30 代码：S-XQCC-N60
JESD-609代码：e3长度：9 mm
最大线性误差 (EL)：0.0488%湿度敏感等级：3
模拟输入通道数量：2位数：12
功能数量：1端子数量：60
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式：SERIAL
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC60,.35SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：3/3.3 V认证状态：Not Qualified
采样速率：105 MHz采样并保持/跟踪并保持：SAMPLE
座面最大高度：0.8 mm子类别：Analog to Digital Converters
最大压摆率：270 mA标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：9 mm

ADC12DS105CISQ/NOPB 数据手册

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ADC12DS105  
www.ti.com  
SNAS382E –SEPTEMBER 2006–REVISED APRIL 2013  
ADC12DS105 Dual 12-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs  
Check for Samples: ADC12DS105  
1
FEATURES  
DESCRIPTION  
The ADC12DS105 is a high-performance CMOS  
analog-to-digital converter capable of converting two  
analog input signals into 12-bit digital words at rates  
up to 105 Mega Samples Per Second (MSPS). The  
digital outputs are serialized and provided on  
differential LVDS signal pairs. This converter uses a  
differential, pipelined architecture with digital error  
correction and an on-chip sample-and-hold circuit to  
minimize power consumption and the external  
component count, while providing excellent dynamic  
performance. The ADC12DS105 may be operated  
from a single +3.0V or 3.3V power supply. A power-  
down feature reduces the power consumption to very  
low levels while still allowing fast wake-up time to full  
operation. The differential inputs accept a 2V full  
scale differential input swing. A stable 1.2V internal  
voltage reference is provided, or the ADC12DS105  
can be operated with an external 1.2V reference. The  
2
•
Clock Duty Cycle Stabilizer  
Single +3.0 or 3.3V Supply Operation  
Serial LVDS Outputs  
•
•
•
•
•
Serial Control Interface  
Overrange Outputs  
60-pin WQFN Package, (9x9x0.8mm, 0.5mm  
pin-pitch)  
APPLICATIONS  
•
•
•
•
•
High IF Sampling Receivers  
Wireless Base Station Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Portable Instrumentation  
selectable  
duty  
cycle  
stabilizer  
maintains  
KEY SPECIFICATIONS  
performance over a wide range of clock duty cycles.  
A serial interface allows access to the internal  
registers for full control of the ADC12DS105's  
functionality. The ADC12DS105 is available in a 60-  
lead WQFN package and operates over the industrial  
temperature range of −40°C to +85°C  
•
•
•
•
•
•
Resolution: 12 Bits  
Conversion Rate: 105 MSPS  
SNR (fIN = 240 MHz): 68.5 dBFS (typ)  
SFDR (fIN = 240 MHz): 83 dBFS (typ)  
Full Power Bandwidth: 1 GHz (typ)  
Power Consumption: 1 W (typ)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006–2013, Texas Instruments Incorporated  
1234567...35

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ADC12DS105CISQ/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
ADC12DS105CISQE/NOPB TI

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