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AD9957_07

更新时间: 2024-11-11 04:04:27
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
60页 1183K
描述
1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC

AD9957_07 数据手册

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1 GSPS Quadrature Digital Upconverter  
with 18-Bit IQ Data Path and 14-Bit DAC  
AD9957  
FEATURES  
GENERAL DESCRIPTION  
1 GSPS internal clock speed (up to 400 MHz analog output)  
Integrated 1 GSPS 14-bit DAC  
The AD9957 functions as a universal I/Q modulator and agile  
upconverter for communications systems where cost, size, power  
consumption, and dynamic performance are critical. The AD9957  
integrates a high speed, direct digital synthesizer (DDS), a high  
performance, high speed, 14-bit digital-to-analog converter (DAC),  
clock multiplier circuitry, digital filters, and other DSP functions  
onto a single chip. It provides for baseband upconversion for data  
transmission in a wired or wireless communications system.  
250 MHz I/Q data throughput rate  
Phase noise ≤ −125 dBc/Hz (400 MHz carrier @ 1 kHz offset)  
Excellent dynamic performance >80 dB narrow-band SFDR  
8 programmable profiles for shift keying  
SIN(x)/(x) correction (inverse sinc filter)  
Reference clock multiplier  
Internal oscillator for a single crystal operation  
Software and hardware controlled power-down  
Integrated RAM  
Phase modulation capability  
Multichip synchronization  
Easy interface to Blackfin SPORT  
Interpolation factors from 4× to 252×  
Interpolation DAC mode  
The AD9957 is the third offering in a family of quadrature  
digital upconverters (QDUCs) that includes the AD9857 and  
AD9856. It offers performance gains in operating speed, power  
consumption, and spectral performance. Unlike its predecessors,  
it supports a 16-bit serial input mode for I/Q baseband data.  
The device can alternatively be programmed to operate either as  
a single tone, sinusoidal source or as an interpolating DAC.  
Gain control DAC  
The reference clock input circuitry includes a crystal oscillator,  
a high speed, divide-by-two input, and a low noise PLL for  
multiplication of the reference clock frequency.  
Internal divider allows references up to 2 GHz  
1.8 V and 3.3 V power supplies  
100-lead TQFP_EP package  
The user interface to the control functions includes a serial port  
easily configured to interface to the SPORT of the Blackfin®  
DSP and profile pins to enable fast and easy shift keying of any  
signal parameter (phase, frequency, and amplitude).  
APPLICATIONS  
HFC data, telephony, and video modems  
Wireless base station transmission  
Broadband communications transmissions  
Internet telephony  
FUNCTIONAL BLOCK DIAGRAM  
I
DATA  
FOR  
XMIT  
FORMAT AND  
INTERPOLATE  
14-BIT DAC  
I/Q DATA  
Q
NCO  
AD9957  
TIMING  
AND  
CONTROL  
REFERENCE CLOCK  
INPUT CIRCUITRY  
USER INTERFACE  
REFERENCE CLOCK INPUT  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2007 Analog Devices, Inc. All rights reserved.  
 

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