4 Channel 500MSPS DDS with 10-bit DACs
Preliminary Technical Data
AD9959
FEATURES
Software/Hardware controlled power-down
Dual supply operation (1.8 V DDS core / 3.3 V serial I/O)
Built-in synchronization for multiple devices
Selectable REF_CLK multipier(PLL) 4x to 20x (bypassable)
Selectable REF_CLK crystal operation
Four synchronized DDS channels @500 MSPS
Independent frequency / phase / amplitude
control between all channels
Matched latencies for Freq, Phase, and Amplitude changes
Excellent channel to channel isolation
56 pin LFCSP package
Frequency sweeping capability
Up to 16 levels of modulation (pin selectable)
Individually programmable DAC full scale currents
Four integrated 10-bit D/A converters(DACs)
32-bit frequency tuning resolution
APPLICATIONS
Agile L.O. frequency synthesis
Phased array radar / sonar
Instrumentation
14-bit phase offset resolution
Synchronized clocking
RF source for AOTF
10-bit output amplitude scaling resolution
Serial I/O Port(SPI) with enhanced data throughput
FUNCTIONAL BLOCK DIAGRAM
DDS CORE
FREQUENCY
ACCUMULATOR
IOUT
IOUT
COS(X)
Σ
Σ
Σ
Σ
Σ
Σ
Σ
Σ
Σ
×
×
×
×
15
DAC
DAC
DAC
DAC
32
32
10
10
10
10
10
10
10
10
DDS CORE
FREQUENCY
ACCUMULATOR
IOUT
IOUT
COS(X)
Σ
15
32
32
32
DDS CORE
FREQUENCY
ACCUMULATOR
IOUT
IOUT
COS(X)
Σ
15
32
DDS CORE
FREQUENCY
ACCUMULATOR
IOUT
IOUT
COS(X)
Σ
15
32
32
RAMP
RATE
SCALABLE
DAC REF
CURRENT
DIGITAL
MULTIPLIER
PHASE
OFFSET
DAC_RSET
14
DFTW
32
FTW
32
10
8
SYNC_IN
SYNC_OUT
I/O_UPDATE
PWR_DWN_CTL
MASTER_RESET
Timing & Control Logic
SYSTEM
CLK
SYNC_CLK
÷4
CONTROL
REGISTERS
SCLK
CS
I/O
Port
Buffer
CHANNEL
REGISTERS
M
U
X
SDIO_0
SDIO_1
SDIO_2
SDIO_3
REF CLOCK
MULTIPLIER
(PLL) 4x to 20x
OSC / REF_CLK
OSC / REF_CLK
PROFILE
REGISTERS
BUFFER / XTAL
OSCILLATOR
3.3V
1.8V
1.8V
AVDD
DVDD
P P P P
S S S S
DVDD_IO
CLK_MODE_SEL
0
1 2 3
Figure 1 AD9959 Block Diagram
Rev. PrB
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