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AD995PCBZ PDF预览

AD995PCBZ

更新时间: 2024-11-11 04:04:27
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亚德诺 - ADI /
页数 文件大小 规格书
38页 618K
描述
1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC

AD995PCBZ 数据手册

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1 GSPS Quadrature Digital Upconverter  
w/18-Bit IQ Data Path and 14-Bit DAC  
AD9957  
PRELIMINARY TECHNICAL DATA  
FEATURES  
GENERAL DESCRIPTION  
1GSPS internal clock speed (up to 400MHz analog out)  
Integrated 1GSPS 14-bit DAC  
The AD9957 functions as a universal I/Q modulator and agile  
upconverter for communications systems where cost, size,  
power consumption and dynamic performance are critical. The  
AD9957 integrates a high speed Direct Digital Synthesizer  
(DDS), a high performance, high speed 14-bit digital to analog  
converter (DAC), clock multiplier circuitry, digital filters and  
other DSP functions onto a single chip. It provides for base  
band up-conversion for data transmission in a wired or wireless  
communications system.  
250 MHz I/Q data throughput rate  
Phase noise ≤ –123 dBc/Hz (400 MHz carrier)  
Excellent dynamic performance >80 dB narrowband SFDR  
8 Programmable Profiles for shift keying  
SIN(X)/(X) Correction (Inverse SINC filter)  
Reference Clock Multiplier  
Internal oscillator for a single crystal operation  
Software and hardware controlled power-down  
Integrated RAM  
The AD9957 is the third offering in a family of a quadrature  
digital upconverters (QDUCs), which includes the AD9857 and  
AD9856. It offers performance gains in operating speed, power  
consumption and spectral performance. Unlike its predeces-  
sors, it also supports a 16-bit serial input mode for I/Q base  
band data. The device can alternatively be programmed to op-  
erate as a single-tone sinusoidal source or as an interpolating  
DAC.  
Phase modulation capability  
Multichip synchronization  
Easy interface to Blackfin™ SPORT  
Interpolation factors from 4x to 252x  
Test tone circuitry  
Interpolation DAC Mode  
Gain control DAC  
Internal divider allows references up to 2 GHz  
1.8V & 3.3V Power Supplies  
100 Lead TQFP package  
The Reference Clock input circuitry includes a crystal oscillator,  
a high speed divide-by-two input, and a low noise PLL for mul-  
tiplication of the reference clock frequency.  
APPLICATIONS  
HFC Data, Telephony & Video Modems  
Wireless Base Station Transmission  
Broadband Communications Transmissions  
Internet Telephony  
The user interface to the control functions includes a serial port  
easily configured to interface to the SPORT of the Blackfin DSP  
and profile pins which enable fast and easy shift keying of any  
signal parameter (phase, frequency, and amplitude).  
Figure 1: Basic Block Diagram  
Rev. PrF  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2006 Analog Devices, Inc. All rights reserved.  

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