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AD9970BCPZRL

更新时间: 2024-11-11 19:06:31
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亚德诺 - ADI 商用集成电路
页数 文件大小 规格书
3页 109K
描述
14-Bit CCD Signal Processor with Precision Timing™ Generator

AD9970BCPZRL 数据手册

 浏览型号AD9970BCPZRL的Datasheet PDF文件第2页浏览型号AD9970BCPZRL的Datasheet PDF文件第3页 
14-Bit CCD Signal Processor with Precision  
Timing™ Generator  
Data Sheet  
AD9970  
FEATURES  
GENERAL DESCRIPTION  
1.8 V analog and digital core supply voltage  
The AD9970 is a highly integrated CCD signal processor for  
Serial data link with reduced range LVDS outputs  
Correlated double sampler (CDS) with −3 dB, 0 dB, +3 dB,  
and +6 dB gain  
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)  
14-bit, 65 MHz ADC  
high speed digital video camera applications. Specified at pixel  
rates of up to 65 MHz, the AD9970 consists of a complete analog  
front end with analog-to-digital conversion combined with a  
programmable timing driver. The Precision Timing core allows  
adjustment of high speed clocks with 240 ps resolution at  
65 MHz operation. The AD9970 also contains a reduced range  
LVDS interface for data outputs.  
Black level clamp with variable level control  
Complete on-chip timing generator  
Precision Timing core with 240 ps resolution at 65 MHz  
On-chip, 3 V horizontal and RG drivers  
5 mm × 5 mm, 32-lead LFCSP_VQ  
The analog front end includes black level clamping, CDS, VGA,  
and a 65 MSPS, 14-bit ADC. The timing driver provides the high  
speed CCD clock drivers for RG, HL, and H1 to H4. Operation  
is programmed using a 3-wire serial interface.  
APPLICATIONS  
Professional HDTV camcorders  
Professional/high end digital cameras  
Broadcast cameras  
Packaged in a space-saving 5 mm × 5 mm, 32-lead LFCSP_VQ,  
the AD9970 is specified over an operating temperature range of  
−25°C to +85°C.  
Industrial high speed cameras  
High speed data acquisition systems  
For more information about the AD9970, contact Analog Devices  
via email at afe.ccd@analog.com.  
FUNCTIONAL BLOCK DIAGRAM  
REFT REFB  
AD9970  
VREF  
–3, 0, +3, +6dB  
CDS  
6dB TO 42dB  
VGA  
TCLKP  
TCLKN  
14-BIT  
ADC  
CCDIN  
REDUCED  
RANGE  
LVDS OUTPUT  
DOUT0P  
DOUT0N  
CLAMP  
DOUT1P  
DOUT1N  
INTERNAL CLOCKS  
RG  
HL  
PRECISION  
TIMING  
GENERATOR  
HORIZONTAL  
DRIVERS  
4
SL  
H1 TO H4  
INTERNAL  
REGISTERS  
SCK  
SDATA  
SYNC  
GENERATOR  
HD VD  
CLI  
Figure 1.  
Rev. SpD  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2005–2014 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  

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