High Performance
10-Bit Display Interface
AD9981
FEATURES
FUNCTIONAL BLOCK DIAGRAM
10-bit analog-to-digital converter
95 MSPS maximum conversion rate
9% or less p-p PLL clock jitter at 95 MSPS
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
10
AUTO OFFSET
AD9981
PR/RED
PR/RED
1
0
10
10
10
10
10
10
IN
2:1
MUX
10-BIT
ADC
RED
OUT
CLAMP
CLAMP
CLAMP
PGA
10
IN
AUTO OFFSET
Y/GREEN
Y/GREEN
1
0
IN
2:1
MUX
10-BIT
ADC
PGA
10
GREEN
OUT
IN
AUTO OFFSET
PB/BLUE
PB/BLUE
1
0
IN
2:1
MUX
10-BIT
ADC
BLUE
PGA
OUT
External clock input
IN
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsyncs counter
HSYNC1
HSYNC2
2:1
MUX
DATACK
SOGOUT
O/E FIELD
HSOUT
SYNC
PROCESSING
VSYNC1
VSYNC2
2:1
MUX
Pb-free package
PLL
POWER
MANAGEMENT
SOGIN1
SOGIN2
2:1
MUX
APPLICATIONS
Advanced TVs
Plasma display panels
LCDTV
VSOUT/A0
EXTCLK/COAST
CLAMP
FILT
REFHI
VOLTAGE
REFS
SDA
SCL
REFCM
REFLO
SERIAL REGISTER
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
Figure 1.
GENERAL DESCRIPTION
The AD9981 is a complete, 10-bit, 95 MSPS, monolithic analog
interface optimized for capturing YPbPr video and RGB
graphics signals. Its 95 MSPS encode rate capability and full-
power analog bandwidth of 200 MHz supports all HDTV
video modes and graphics resolutions up to XGA (1024 × 768
at 85 Hz).
With internal Coast generation, the PLL maintains its output
frequency in the absence of sync input. A 32-step sampling
clock phase adjustment is provided. Output data, sync, and
clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The AD9981 also
offers full sync processing for composite sync and sync-on-
green applications. A clamp signal is generated internally or
may be provided by the user through the CLAMP input pin.
The AD9981 includes a 95 MHz triple ADC with an internal
reference, a PLL, programmable gain, offset, and clamp controls.
The user provides only 3.3 V and 1.8 V power supplies and an
analog input. Three-state CMOS outputs may be powered from
1.8 V to 3.3 V.
Fabricated in an advanced CMOS process, the AD9981 is
provided in a space-saving, 80-pin, Pb-free, LQFP surface
mount plastic package. It is specified over the 0°C to +70°C
temperature range.
The AD9981’s on-chip PLL generates a sample clock from
the three-level sync (for YPbPr video) or the horizontal sync
(for RGB graphics). Sample clock output frequencies range from
10 MHz to 95 MHz. PLL clock jitter is 9% or less p-p typical at
95 MSPS.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
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