High Performance
10-Bit Display Interface
AD9984A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
10-bit, analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
AD9984A
10
AUTO OFFSET
AUTO GAIN
Pr/RED
Pr/RED
10
10
10
IN1
IN0
2:1
MUX
10-BIT
ADC
Cb/Cr/RED
CLAMP
CLAMP
CLAMP
PGA
PGA
PGA
OUT
10
10
AUTO OFFSET
AUTO GAIN
Y/GREEN
Y/GREEN
IN1
2:1
MUX
10-BIT
ADC
Y/GREEN
OUT
IN0
AUTO OFFSET
AUTO GAIN
External clock input
Regenerated Hsync output
Pb/BLUE
Pb/BLUE
IN1
2:1
MUX
10-BIT
ADC
Cb/BLUE
OUT
IN0
Programmable output high impedance control
Hsyncs per Vsync counter
Sync-on-green (SOG) pulse filter
Pb-free package
HSYNC1
HSYNC0
2:1
MUX
DATACK
SOGOUT
SYNC
VSYNC0
VSYNC1
2:1
MUX
PROCESSING
ODD/EVEN FIELD
HSOUT
PLL
POWER
MANAGEMENT
APPLICATIONS
SOGIN1
SOGIN0
2:1
MUX
VSOUT/A0
Advanced TVs
Plasma display panels
LCDTV
EXTCK/COAST
CLAMP
REFHI
FILT
VOLTAGE
REFS
REFLO
SDA
SCL
SERIAL REGISTER
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
Figure 1.
GENERAL DESCRIPTION
The AD9984A is a complete 10-bit, 170 MSPS, monolithic
analog interface optimized for capturing YPbPr video and RGB
graphics signals. Its 170 MSPS encode rate capability and full
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080p, as well as graphics resolutions up to UXGA
(1600 × 1200 at 60 Hz).
sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and calibrate out any offset differences
between the three channels. The auto channel-to-channel gain-
matching feature can be enabled to minimize any gain
mismatches between the three channels.
The AD9984A includes a 170 MHz triple ADC with an internal
reference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a 1.8 V power supply and an
analog input. Three-state CMOS outputs can be powered from
1.8 V to 3.3 V.
The AD9984A also offers full sync processing for composite sync
and sync-on-green applications. A clamp signal is generated
internally or can be provided by the user through the CLAMP
input pin.
The AD9984A on-chip PLL generates a sample clock from the
tri-level sync (for YPbPr video) or the horizontal sync (for RGB
graphics). Sample clock output frequencies range from 10 MHz
to 170 MHz. With internal coast generation, the PLL maintains
its output frequency in the absence of a sync input. A 32-step
Fabricated in an advanced CMOS process, the AD9984A is
provided in a space-saving, Pb-free, 80-lead low profile quad
flat package (LQFP) or 64-lead lead frame chip scale package
(LFCSP) and is specified over the 0°C to 70°C temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
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