Data Sheet
AD9986
4T2R Direct RF Transmitter and Observation Receiver
FEATURES
APPLICATIONS
► Flexible reconfigurable radio common platform design
► Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz
(4T2R)
► RFDAC/RFADC RF frequency range up to 7.5 GHz
► On-chip PLL with multichip synchronization
► External RFCLK input option
► Versatile digital features
► Configurable digital up/down conversion (DDC and DUC)
► 8 fine complex DUCs and 4 coarse complex DUCs
► Wireless communications infrastructure
► W-CDMA, LTE, LTE-A, Massive-MIMO
► Microwave point-to-point, E-band, and 5G mm Wave
► Broadband communications systems
► DOCSIS 3.1 and 4.0 CMTS
► Communications test and measurement system
GENERAL DESCRIPTION
The AD9986 is a highly integrated device with a 16-bit, 12 GSPS
maximum sample rate RF DAC core, and a 12-bit, 6 GSPS rate
RF ADC core. The AD9986 supports four transmitter channels and
two receiver channels with four transmitter, two receiver (4T2R)
configuration. The AD9986 is well suited for 2-antenna and
4-antenna transmitter applications requiring a wide bandwidth ob-
servation receiver path for the digital predistortion. The AD9986
supports up to a 6 GSPS complex transmit and receive data rate
in single channel mode. The maximum radio channel bandwidth
supported is 1.2 GHz and 2.4 GHz for the transmit and receive
paths, respectively (4T2R). The AD9986 features a 16 lane, 24.75
Gbps JESD204C or 15.5 Gbps JESD204B serial data port, an
on-chip clock multiplier, and digital signal processing capability
targeted at multiband, direct-to-RF radio applications.
► 8 fine complex DDCs and 4 coarse complex DDCs, 2
independent
► 48-bit NCO per DUC/DDC
► Programmable 192-tap PFIR filter for receive equalization
► Supports 4 different profile settings loaded via GPIO
► Receive AGC support
► Fast detect with low latency for fast AGC control
► Signal monitor for slow AGC control
► Dedicated AGC support pins
► Transmit DPD support
► Programmable delay and gain per transmit data path
► Coarse DDC delay adjust for DPD observation path
► Auxiliary features
► Power amplifier downstream protection circuitry
► On-chip temperature monitoring unit
► Programmable GPIO pins supporting different user configura-
tions
► ADC clock driver with selectable divide ratios
► TDD power savings option and sharing ADCs
► SERDES JESD204B/JESD204C interface, 16 lanes up to
24.75 Gbps
► 8 lanes per each DAC and ADC
► JESD204B compatible with maximum 15.5 Gbps lane rate
► JESD204C compatible with maximum 24.75 Gbps lane rate
► Supports real or complex digital data (8-bit, 12-bit, 16-bit, or
24-bit)
► 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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