Datasheet > AD9986

AD9986

更新时间： 2023-12-20 18:46:29

品牌	Logo	应用领域
亚德诺 - ADI		接收机
页数	文件大小	规格书
37页	3570K
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4T2R直接RF发射器和观测接收机

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AD9986 数据手册

Data Sheet

AD9986

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Successful DAC calibration is required during the device initialization phase that occurs shortly after power-up to ensure long-term reliability of

the DAC core circuitry. Refer to UG-1578, the device user guide, for more information on device initialization.

Table 1.

Parameter

Min

Typ

Max

Unit

OPERATING JUNCTION TEMPERATURE (T_J)

ANALOG SUPPLY VOLTAGE RANGE

AVDD2, BVDD2, RVDD2

−40

+120

°C

1.9

2.0

1.0

2.1

AVDD1, AVDD1_ADC, CLKVDD1, FVDD1, VDD1_NVG

DIGITAL SUPPLY VOLTAGE RANGE

DVDD1, DVDD1_RT, DCLKVDD1, DAVDD1

DVDD1P8

0.95

1.05

0.95

1.7

1.0

1.8

1.05

2.1

SERIALIZER/DESERIALIZER (SERDES) SUPPLY VOLTAGE RANGE

SVDD2_PLL

1.9

2.0

1.0

2.1

SVDD1, SVDD1_PLL

0.95

1.05

POWER CONSUMPTION

Typical at nominal supplies and maximum at 5% supplies. For the minimum and maximum values, T_Jvaries between −40°C and +120°C. For

the typical values, T_A= 25°C, which corresponds to T_J= 80°C, unless otherwise noted.

DAC datapath with a complex I/Q data rate frequency (f_{IQ_DATA}) = 1500 MSPS, interpolation of 8×, and DAC frequency (f_DAC) of 12 GSPS. JRx

mode of 15C (L = 8, M = 8, F = 2, S = 1, K = 128, E = 1, N = 16, NP = 16).

ADC datapath with a complex f_{IQ_DATA}= 3000 MSPS, decimation of 2×, and ADC sample rate (f_ADC) of 6 GSPS. JTx mode of 18C (L = 8, M = 4,

F = 1, S = 1, K = 128, E = 1, N = 16, NP = 16).

Note that the AD9986 does not have the option to bypass the digital up and down converters in the transmit and receive paths, respectively.

See the UG-1578 for further information on the JESD204B and JESD204C mode configurations, and a detailed description of the settings

referenced throughout this data sheet.

Table 2.

Parameter

Test Conditions/Comments

Min Typ

Max

Unit

CURRENTS

AVDD2 (I_AVDD2

)

2.0 V supply

195

290

204

340

BVDD2 (I_BVDD2) + RVDD2 (I_RVDD2

)

2.0 V supply

AVDD2_PLL (I_{AVDD2__PLL}) + SVDD2_PLL (I_{SVDD2__PLL}

Power Dissipation for 2 V Supplies

)

2.0 V supply

2.0 V supply total power dissipation

1.0 V supply

1.06

1.20

PLLCLKVDD1 (I_PLLCLKVDD1

AVDD1 (I_AVDD1) + DCLKVDD1 (I_DCLKVDD1

AVDD1_ADC (I_{AVDD1_ADC}

CLKVDD1 (I_CLKVDD1

FVDD1 (I_FVDD1

VDD1_NVG (I_{VDD1_NVG}

DAVDD1 (I_DAVDD1

DVDD1 (I_DVDD1

DVDD1_RT (I_{DVDD1_RT}

)

1.0 V supply

975

1725

1180

2100

150

)

1.0 V supply

)

1.0 V supply

)

1.0 V supply

)

1.0 V supply

280

1575

3010

630

1875

10.22

360

1840

4070

760

2510

13.08

)

1.0 V supply

)

1.0 V supply

)

1.0 V supply

SVDD1 (I_SVDD1) + SVDD1_PLL (I_{SVDD1_PLL}

Power Dissipation for 1 V Supplies

)

1.0 V supply

1.0 V supply total power dissipation

1.8 V supply

DVDD1P8 (I_DVDD1P8

)

analog.com

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