Integrated Mixed-Signal Front End (MxFE)
Data Sheet
AD9993
FEATURES
GENERAL DESCRIPTION
Quad 14-bit 250 MSPS ADC
SFDR = 83 dBc at 87 MHz input
Dual 14-bit 500 MSPS DAC
SFDR = 75 dBc at 20 MHz output
On-chip PLL clock synthesizer
Low power
The AD9993 is a mixed-signal front-end (MxFE®) device that
integrates four 14-bit ADCs and two 14-bit DACs. Figure 1
shows the block diagram of the MxFE. The MxFE is
programmable using registers accessed via a serial peripheral
interface (SPI). ADC and DAC datapaths include FIFO buffers
to absorb phase differences between LVDS lane clocks and the
1536 mW, 1 GHz master clock, on-chip synthesizer
500 MHz double data rate (DDR)
LVDS interfaces for DACs and ADCs
data converter sampling clocks.
The MxFE DACs are part of the Analog Devices, Inc., high
speed CMOS DAC core family. These DACs are designed to be
used in wide bandwidth communication system transmitter
(Tx) signal chains.
Small 12 mm × 12 mm lead-free BGA package
APPLICATIONS
Point to point microwave backhaul radios
Wireless repeaters
The MxFE ADCs are multistage pipelined CMOS ADC cores
designed for use in communications receivers.
FUNCTIONAL BLOCK DIAGRAM
DOUT3A_x TO DOUT0A_x
DOUT3B_x TO DOUT0B_x
DOUT3C_x TO DOUT0C_x
DOUT3D_x TO DOUT0D_x
DCO_x
2
2
2
2
14
14
14
14
14
4
ADC_A
ADC_B
ADC_C
ADC_D
LVDS
BUFFER
DCO CLOCK
STROBE
STROBE_x
DIGITAL
–ADC AND DAC
DATAPATHS
–CONTROLS
–SPI REGISTERS
–FIFO BUFFERS
14
DIN6A_x TO DIN0A_x
LVDS
BUFFER
DIN6B_x TO DIN0B_x
DCI_x
DCI CLOCK
2
2
14
14
DAC_A
DAC_B
4
SPI_SCLK, SPI_CS, SPI_SDI, SPI_SDO
RST
ALERT
PLL
0
1
MxFE
AD9993
CLOCK GENERATOR
31.25MHz
OR
62.5MHz
DIV
1GHz
Figure 1.
Rev. A
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