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AD9959YSV-REEL7 PDF预览

AD9959YSV-REEL7

更新时间: 2024-11-11 20:04:07
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
41页 672K
描述
IC,FREQUENCY SYNTHESIZER,CMOS,LLCC,56PIN,PLASTIC

AD9959YSV-REEL7 数据手册

 浏览型号AD9959YSV-REEL7的Datasheet PDF文件第2页浏览型号AD9959YSV-REEL7的Datasheet PDF文件第3页浏览型号AD9959YSV-REEL7的Datasheet PDF文件第4页浏览型号AD9959YSV-REEL7的Datasheet PDF文件第5页浏览型号AD9959YSV-REEL7的Datasheet PDF文件第6页浏览型号AD9959YSV-REEL7的Datasheet PDF文件第7页 
4 Channel 500MSPS DDS with 10-bit DACs  
Preliminary Technical Data  
AD9959  
FEATURES  
Four synchronized DDS channels @500 MSPS  
Independent Frequency/Phase/Amplitude  
control between channels  
Software/Hardware controlled power-down  
Dual supply operation (1.8 V DDS core / 3.3 V serial I/O)  
Built-in synchronization for multiple devices  
Selectable REF_CLK multipier (PLL) 4x to 20x (bypassable)  
Selectable REF_CLK crystal operation  
Matched latencies for Frequency/Phase/Amplitude changes  
Excellent channel to channel isolation (>60dB)  
Linear Frequency/Phase/Amplitude sweeping capability  
56 pin LFCSP package  
Up to 16 levels of Frequency/Phase/Amplitude modulation (pin  
selectable P0-P3)  
APPLICATIONS  
Individually programmable DAC full scale currents  
Four integrated 10-bit D/A converters (DACs)  
32-bit Frequency tuning resolution  
Agile L.O. frequency synthesis  
Phased array radar / sonar  
Instrumentation  
14-bit Phase Offset resolution  
Synchronized clocking  
RF source for AOTF  
10-bit Output Amplitude Scaling resolution  
Serial I/O Port (SPI) with enhanced data throughput  
FUNCTIONAL BLOCK DIAGRAM  
DDS CORE  
IOUT  
IOUT  
COS(X)  
Σ
Σ
Σ
Σ
Σ
Σ
Σ
Σ
Σ
×
×
×
×
15  
32  
32  
DAC  
DAC  
DAC  
DAC  
10  
10  
10  
10  
10  
10  
10  
10  
DDS CORE  
IOUT  
IOUT  
COS(X)  
Σ
Σ
Σ
15  
32  
32  
32  
32  
DDS CORE  
IOUT  
IOUT  
COS(X)  
15  
DDS CORE  
IOUT  
IOUT  
COS(X)  
15  
32  
32  
SCALABLE  
DAC REF  
CURRENT  
PHASE /  
PHASE  
AMP /  
AMP  
DAC_RSET  
FTW  
32  
14  
10  
FTW  
SYNC_IN  
SYNC_OUT  
I/O_UPDATE  
TIMING & CONTROL LOGIC  
PWR_DWN_CTL  
MASTER_RESET  
SYSTEM  
CLK  
SYNC_CLK  
CONTROL  
REGISTERS  
÷4  
SCLK  
CS  
I/O  
Port  
Buffer  
CHANNEL  
REGISTERS  
M
U
X
REF CLOCK  
MULTIPLIER  
4x to 20x  
SDIO_0  
SDIO_1  
SDIO_2  
SDIO_3  
REF_CLK  
REF_CLK  
PROFILE  
REGISTERS  
BUFFER / XTAL  
OSCILLATOR  
1.8V  
1.8V  
3.3V  
P
S
0
P P  
S S  
P
S
3
AVDD  
DVDD  
DVDD_I/O  
CLK_MODE_SEL  
1
2
Figure 1 AD9959 Block Diagram  
Rev. PrD  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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