12-Bit, 200 MSPS/500 MSPS TxDAC+® with
2×/4×/8× Interpolation and Signal Processing
Preliminary Technical Data
AD9782
PRODUCT DESCRIPTION
FEATURES
12-bit resolution, 200 MSPS input data rate
Selectable 2×/4×/8× interpolation filters
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
SFDR 90 dBc @10 MHz
The AD9782 is a 12-bit, high speed, CMOS DAC with 2×/4×/8×
interpolation and signal processing features tuned for
communications applications. It offers state of the art distortion
and noise performance. The AD9782 was developed to meet the
demanding performance requirements of multicarrier and third
generation base stations. The selectable interpolation filters
simplify interfacing to a variety of input data rates while also
taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = 0.75 LSB
INL = 1.5 LSB
3.3 V compatible digital Interface
On-chip 1.2 V reference
The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single ended or
differential mode. Internal dividers generate the required data
rate interface clocks.
80-lead thermally enhanced TQFP package
The AD9782 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9782 is
manufactured on an advanced low cost 0.25 µm CMOS process.
APPLICATIONS
Digital quadrature modulation architectures
Multicarrier WCDMA, GSM, TDMA, DCS,
PCS, CDMA Systems
FUNCTIONAL BLOCK DIAGRAM
LATCH
2×
2×
2×
I
FSADJ
REFIO
0
0
∆t
90
90
P1B[15:0]
P2B[15:0]
f
f
f
/2
/4
/8
DAC
DAC
DAC
0
I
ZERO
STUFF
OUTA
16-BIT DAC
90
I
OUTB
SDIO
SDO
HILBERT
CSB
SCLK
RESET
Q
×1
DATACLK/
PLL_LOCK
LATCH
2×
2×
2×
×2
×4
×8
CLK+
CLK–
LPF
CLOCK DISTRIBUTION AND CONTROL
Figure 1.
Rev. PrC
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