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AD9782 PDF预览

AD9782

更新时间: 2024-09-12 22:25:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
52页 1615K
描述
12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing

AD9782 数据手册

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12-Bit, 200 MSPS/500 MSPS TxDAC+® with  
2×/4×/8× Interpolation and Signal Processing  
Preliminary Technical Data  
AD9782  
PRODUCT DESCRIPTION  
FEATURES  
12-bit resolution, 200 MSPS input data rate  
Selectable 2×/4×/8× interpolation filters  
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes  
Single or dual-channel signal processing  
Selectable image rejection Hilbert transform  
Flexible calibration engine  
Direct IF transmission features  
Serial control interface  
Versatile clock and data interface  
SFDR 90 dBc @10 MHz  
The AD9782 is a 12-bit, high speed, CMOS DAC with 2×/4×/8×  
interpolation and signal processing features tuned for  
communications applications. It offers state of the art distortion  
and noise performance. The AD9782 was developed to meet the  
demanding performance requirements of multicarrier and third  
generation base stations. The selectable interpolation filters  
simplify interfacing to a variety of input data rates while also  
taking advantage of oversampling performance gains. The  
modulation modes allow convenient bandwidth placement and  
selectable sideband suppression.  
WCDMA ACLR = 80 dBc @ 40 MHz IF  
DNL = 0.75 LSB  
INL = 1.5 LSB  
3.3 V compatible digital Interface  
On-chip 1.2 V reference  
The flexible clock interface accepts a variety of input types such  
as 1 V p-p sine wave, CMOS, and LVPECL in single ended or  
differential mode. Internal dividers generate the required data  
rate interface clocks.  
80-lead thermally enhanced TQFP package  
The AD9782 provides a differential current output, supporting  
single-ended or differential applications; it provides a nominal  
full-scale current from 10 mA to 20 mA. The AD9782 is  
manufactured on an advanced low cost 0.25 µm CMOS process.  
APPLICATIONS  
Digital quadrature modulation architectures  
Multicarrier WCDMA, GSM, TDMA, DCS,  
PCS, CDMA Systems  
FUNCTIONAL BLOCK DIAGRAM  
LATCH  
2×  
2×  
2×  
I
FSADJ  
REFIO  
0
0
t  
90  
90  
P1B[15:0]  
P2B[15:0]  
f
f
f
/2  
/4  
/8  
DAC  
DAC  
DAC  
0
I
ZERO  
STUFF  
OUTA  
16-BIT DAC  
90  
I
OUTB  
SDIO  
SDO  
HILBERT  
CSB  
SCLK  
RESET  
Q
×1  
DATACLK/  
PLL_LOCK  
LATCH  
2×  
2×  
2×  
×2  
×4  
×8  
CLK+  
CLK–  
LPF  
CLOCK DISTRIBUTION AND CONTROL  
Figure 1.  
Rev. PrC  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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