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AD9786BSVZRL PDF预览

AD9786BSVZRL

更新时间: 2024-11-05 12:33:19
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器
页数 文件大小 规格书
56页 1527K
描述
16-Bit, 200 MSPS/500 MSPS TxDAC

AD9786BSVZRL 数据手册

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16-Bit, 200 MSPS/500 MSPS TxDAC+® with  
2×/4×/8× Interpolation and Signal Processing  
AD9786  
FEATURES  
PRODUCT HIGHLIGHTS  
16-bit resolution, 200 MSPS input data rate  
IMD 90 dBc @10 MHz  
1. 16-bit, high speed, interpolating TxDAC+.  
2. 2×/4×/8× user-selectable interpolating filter. The filter  
eases data rate and output signal reconstruction filter  
requirements.  
Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz  
WCDMA ACLR = 80 dBc @ 40 MHz IF  
DNL = 0.3 LSB  
INL = 0.6 LSB  
3. 200 MSPS input data rate.  
Selectable 2×/4×/8× interpolation filters  
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes  
Single- or dual-channel signal processing  
Selectable image rejection Hilbert transform  
Flexible calibration engine  
4. Ultra high speed, 500 MSPS DAC conversion rate.  
5. Flexible clock with single-ended or differential input.  
CMOS, 1 V p-p sine wave, and LVPECL capability.  
Direct IF transmission features  
Serial control interface  
Versatile clock and data interface  
3.3 V-compatible digital interface  
On-chip 1.2 V reference  
6. Complete CMOS DAC function. It operates from a 3.1 V  
to 3.5 V single analog (AVDD) supply, 2.5 V digital supply,  
and a 3.3 V digital (DRVDD) supply. The DAC full-scale  
current can be reduced for lower power operation, and  
a sleep mode is provided for low power idle periods.  
80-lead, thermally enhanced, TQFP_EP package  
7. On-chip voltage reference. The AD9786 includes a  
1.20 V temperature-compensated band gap voltage  
reference.  
APPLICATIONS  
Base stations: multicarrier WCDMA, GSM/EDGE, TD-SCDMA,  
IS136, TETRA  
Instrumentation  
RF signal generators, arbitrary waveform generators  
HDTV transmitters  
8. Multichip synchronization. Multiple AD9786 DACs can  
be synchronized to a single master AD9786 to ease timing  
design requirements and optimize image reject transmit  
performance.  
Broadband wireless systems  
Digital radio links  
Satellite systems  
FUNCTIONAL BLOCK DIAGRAM  
LATCH  
2×  
2×  
2×  
FSADJ  
I
REFIO  
0
Δt  
90  
P1B[15:0]  
P2B[15:0]  
IOUTA  
IOUTB  
ZERO  
STUFF  
f
f
f
/2  
/4  
/8  
DAC  
DAC  
DAC  
16-BIT DAC  
0
90  
SDIO  
SDO  
0
HILBERT  
90  
CSB  
Q
SCLK  
RESET  
×1  
DATACLK  
LATCH  
2×  
2×  
2×  
CLK+  
CLK–  
CLOCK DISTRIBUTION AND CONTROL  
Figure 1.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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