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AD9786BSV PDF预览

AD9786BSV

更新时间: 2024-11-04 22:37:07
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
60页 1492K
描述
16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing

AD9786BSV 数据手册

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16-Bit, 200 MSPS/500 MSPS TxDAC+® with  
2×/4×/8× Interpolation and Signal Processing  
AD9786  
FEATURES  
PRODUCT DESCRIPTION  
16-bit resolution, 200 MSPS input data rate  
IMD 90 dBc @10 MHz  
Noise spectral density (NSD) −164 dBm/Hz @ 10 MHz  
WCDMA ACLR = 80 dBc @ 40 MHz IF  
DNL = 0.3 LSB  
The AD9786 is a 16-bit, high speed, CMOS DAC with 2×/4×/8×  
interpolation and signal processing features tuned for com-  
munications applications. It offers state-of-the-art distortion  
and noise performance. The AD9786 was developed to meet the  
demanding performance requirements of multicarrier and third  
generation base stations. The selectable interpolation filters  
simplify interfacing to a variety of input data rates while also  
taking advantage of oversampling performance gains. The  
modulation modes allow convenient bandwidth placement and  
selectable sideband suppression.  
INL = 0.6 LSB  
Selectable 2×/4×/8× interpolation filters  
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes  
Single or dual channel signal processing  
Selectable image rejection Hilbert transform  
Flexible calibration engine  
The flexible clock interface accepts a variety of input types such  
as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or  
differential mode. Internal dividers generate the required data  
rate interface clocks.  
Direct IF transmission features  
Serial control interface  
Versatile clock and data interface  
3.3 V compatible digital interface  
On-chip 1.2 V reference  
The AD9786 provides a differential current output, supporting  
single-ended or differential applications; it provides a nominal  
full-scale current from 10 mA to 20 mA. The AD9786 is  
manufactured on an advanced low cost 0.25 µm CMOS process.  
80-lead thermally enhanced TQFP package  
APPLICATIONS  
Base stations: Multicarrier WCDMA, GSM/EDGE, TD-SCDMA,  
IS136, TETRA  
Instrumentation: RF Signal Generators, Arbitrary Waveform  
Generators  
HDTV Transmitters  
Broadband Wireless Systems  
Digital Radio Links  
Satellite Systems  
FUNCTIONAL BLOCK DIAGRAM  
LATCH  
2×  
2×  
2×  
FSADJ  
Q
REFIO  
0
t  
90  
P1B[15:0]  
P2B[15:0]  
I
I
ZERO  
STUFF  
f
f
f
/2  
/4  
/8  
OUTA  
OUTB  
DAC  
DAC  
DAC  
16-BIT DAC  
0
90  
SDIO  
SDO  
0
HILBERT  
90  
CSB  
Q
SCLK  
RESET  
×1  
DATACLK  
LATCH  
2×  
2×  
2×  
CLK+  
CLK–  
CLOCK DISTRIBUTION AND CONTROL  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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