Datasheet > AD9690BCPZ-500

AD9690BCPZ-500

更新时间： 2024-11-05 01:03:07

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
77页	2250K
描述
14-Bit, 1 GSPS/500 MSPS JESD204B, Analog-to-Digital Converter

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AD9690BCPZ-500 数据手册

14-Bit, 1 GSPS/500 MSPS JESD204B,

Analog-to-Digital Converter

AD9690

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD

SPIVDD

JESD204B (Subclass 1) coded serial digital outputs

2.0 W total power at 1 GSPS (default settings)

1.5 W total power at 500 MSPS (default settings)

SFDR = 85 dBFS at 340 MHz, 80 dBFS at 985 MHz

SNR = 65.3 dBFS at 340 MHz (A_IN= −1.0 dBFS),

60.5 dBFS at 985 MHz

(1.25V) (2.5V) (3.3V)

(1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)

BUFFER

VIN+

VIN–

ADC

SERDOUT0±

CORE

SERDOUT1±

SERDOUT2±

SERDOUT3±

DDC

ENOB = 10.8 bits at 10 MHz

DNL = 0.5 LSB

INL = 2.5 LSB

Noise density = −154 dBFS/Hz at 1 GSPS

1.25 V, 2.5 V, and 3.3 V dc supply operation

No missing codes

Internal ADC voltage reference

Flexible input range

AD9690-1000: 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)

AD9690-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)

Programmable termination impedance

400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

2 GHz usable analog input full power bandwidth

Amplitude detect bits for efficient AGC implementation

2 integrated wideband digital processors

12-bit NCO, up to 4 cascaded half-band filters

Differential clock input

CONTROL

REGISTERS

V_1P0

FAST

DETECT

SYNCINB±

SYSREF±

JESD204B

SUBCLASS 1

CONTROL

CLOCK

GENERATION

CLK+

CLK–

÷2

÷4

÷8

SPI CONTROL

PDWN/

STBY

AD9690

AGND DRGND DGND SDIO SCLK CSB

Figure 1.

PRODUCT HIGHLIGHTS

1. Wide full power bandwidth supports IF sampling of signals

up to 2 GHz.

Integer clock divide by 1, 2, 4, or 8

Flexible JESD204B lane configurations

Small signal dither

2. Buffered inputs with programmable input termination eases

filter design and implementation.

3. Two integrated wideband decimation filters and numerically

controlled oscillator (NCO) blocks supporting multiband

receivers.

4. Flexible serial port interface (SPI) controls various product

features and functions to meet specific system requirements.

5. Programmable fast overrange detection.

6. 9 mm × 9 mm, 64-lead LFCSP.

APPLICATIONS

Communications

Multiband, multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, GSM, LTE

General-purpose software radios

Ultrawideband satellite receivers

Instrumentation

Radars

Signals intelligence (SIGINT)

DOCSIS 3.0 CMTS upstream receive paths

HFC digital reverse path receivers

Wideband digital predistortion

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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与AD9690BCPZ-500相关器件

型号	品牌	获取价格	描述	数据表
AD9690BCPZRL7-1000	ADI	获取价格	14-Bit, 500 MSPS / 1 GSPS JESD204B, Analog-to-Digital Converter
AD9690BCPZRL7-500	ADI	获取价格	14-Bit, 1 GSPS/500 MSPS JESD204B, Analog-to-Digital Converter
AD9691	ADI	获取价格	Dual Analog-to-Digital Converter
AD9691_17	ADI	获取价格	Dual Analog-to-Digital Converter
AD9691-1250EBZ	ADI	获取价格	Dual Analog-to-Digital Converter
AD9691BCPZ-1250	ADI	获取价格	14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter
AD9691BCPZRL7-1250	ADI	获取价格	Dual Analog-to-Digital Converter
AD9694	ADI	获取价格	14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter
AD9694-500EBZ	ADI	获取价格	14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter
AD9694BCPZ-500	ADI	获取价格	Quad 14-Bit, 500 MSPS, 1.2 V/2.5 V Analog-to-Digital Converter

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