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AD9691BCPZRL7-1250 PDF预览

AD9691BCPZRL7-1250

更新时间: 2024-11-05 01:07:43
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亚德诺 - ADI /
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描述
Dual Analog-to-Digital Converter

AD9691BCPZRL7-1250 数据手册

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14-Bit, 1.25 GSPS JESD204B,  
Dual Analog-to-Digital Converter  
AD9691  
Data Sheet  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
AVDD1 AVDD2 AVDD3 AVDD_SR DVDD DRVDD  
SPIVDD  
JESD204B (Subclass 1) coded serial digital outputs  
1.9 W total power per channel (default settings)  
SFDR = 77 dBFS at 340 MHz  
SNR = 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS)  
Noise density = −152.6 dBFS/Hz  
1.25 V, 2.50 V, and 3.3 V dc supply operation  
No missing codes  
1.58 V p-p differential full scale input voltage  
Flexible termination impedance  
(1.25V) (2.50V) (3.3V)  
(1.25V)  
(1.25V) (1.25V) (1.8V TO 3.3V)  
BUFFER  
VIN+A  
VIN–A  
ADC  
14  
CORE  
DIGITAL  
SERDOUT0±  
SERDOUT1±  
SERDOUT2±  
SERDOUT3±  
SERDOUT4±  
SERDOUT5±  
SERDOUT6±  
SERDOUT7±  
DOWN-  
CONVERTER  
8
FD_A  
SIGNAL  
MONITOR  
DIGITAL  
DOWN-  
CONVERTER  
FD_B  
14  
VIN+B  
VIN–B  
ADC  
CORE  
CONTROL  
REGISTERS  
BUFFER  
FAST  
DETECT  
V_1P0  
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential  
1.5 GHz usable analog input full power bandwidth  
95 dB channel isolation/crosstalk  
Amplitude detection bits for efficient AGC implementation  
2 integrated wideband digital processors per channel  
12-bit NCO, up to 4 cascaded half-band filters  
Integer clock divide by 1, 2, 4, or 8  
AD9691  
SIGNAL  
SYNCINB±  
SYSREF±  
JESD204B  
SUBCLASS 1  
CONTROL  
MONITOR  
CLOCK  
GENERATION  
CLK+  
CLK–  
SPI CONTROL  
÷2  
÷4  
÷8  
PDWN/  
STBY  
AGND DRGND DGND  
SDIO SCLK CSB  
Figure 1.  
Flexible JESD204B lane configurations  
Timestamp feature  
Small signal dither  
APPLICATIONS  
Communications (wideband receivers and digital predistortion)  
Instrumentation (spectrum analyzers, network analyzers,  
integrated RF test solutions)  
DOCSIS 3.x CMTS upstream receive paths  
High speed data acquisition systems  
this threshold indicator has low latency, the user can quickly  
turn down the system gain to avoid an overrange condition at  
the ADC input.  
Users can configure the Subclass 1 JESD204B-based high speed  
serialized output in a variety of one-, two-, four- or eight-lane  
configurations, depending on the DDC configuration and the  
acceptable lane rate of the receiving logic device. Multiple device  
synchronization is supported through the SYSREF input pins.  
GENERAL DESCRIPTION  
The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter  
(ADC). The device has an on-chip buffer and sample-and-hold  
circuit designed for low power, small size, and ease of use. The  
device is designed for sampling wide bandwidth analog signals  
of up to 1.5 GHz.  
The AD9691 is available in a Pb-free, 88-lead LFCSP and is  
specified over the −40°C to +85°C industrial temperature range.  
This product is protected by a U.S. patent.  
The dual ADC cores feature a multistage, differential pipelined  
architecture with integrated output error correction logic. Each  
ADC features wide bandwidth inputs supporting a variety of  
user-selectable input ranges. An integrated voltage reference  
eases design considerations.  
PRODUCT HIGHLIGHTS  
1. Low power consumption analog core, 14-bit, 1.25 GSPS  
dual ADC with 1.9 W per channel.  
2. Wide full power bandwidth supports intermediate  
frequency (IF) sampling of signals up to 1.5 GHz.  
3. Buffered inputs with programmable input termination  
eases filter design and implementation.  
4. Flexible serial port interface (SPI) controls various product  
features and functions to meet specific system requirements.  
5. Programmable fast overrange detection.  
Each ADC data output is internally connected to two digital  
downconverters (DDCs). Each DDC consists of four cascaded  
signal processing stages: a 12-bit frequency translator (NCO)  
and four half-band decimation filters.  
In addition to the DDC blocks, the AD9691 has a programmable  
threshold detector that allows monitoring of the incoming  
signal power using the fast detect output bits of the ADC. Because  
6. 12 mm × 12 mm, 88-lead LFCSP.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2015 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 
 

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