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AD9694-500EBZ PDF预览

AD9694-500EBZ

更新时间： 2024-11-05 01:12:35
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亚德诺 - ADI /
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101页 2749K
描述
14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter

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AD9694-500EBZ 数据手册

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14-Bit, 500 MSPS JESD204B,  
Quad Analog-to-Digital Converter  
AD9694  
Data Sheet  
Amplitude detect bits for efficient AGC implementation  
4 integrated wideband digital processors  
48-bit NCO, up to 4 cascaded half-band filters  
Differential clock input  
Integer clock divide by 1, 2, 4, or 8  
On-chip temperature diode  
FEATURES  
JESD204B (Subclass 1) coded serial digital outputs  
Lane rates up to 15 Gbps  
1.66 W total power at 500 MSPS  
415 mW per analog-to-digital converter (ADC) channel  
SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range)  
SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range)  
Noise density = −151.5 dBFS/Hz (1.80 V p-p input range)  
0.975 V, 1.8 V, and 2.5 V dc supply operation  
No missing codes  
Internal ADC voltage reference  
Analog input buffer  
On-chip dithering to improve small signal linearity  
Flexible differential input range  
1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)  
1.4 GHz analog input full power bandwidth  
Flexible JESD204B lane configurations  
APPLICATIONS  
Communications  
Diversity multiband, multimode digital receivers  
3G/4G, W-CDMA, GSM, LTE, LTE-A  
General-purpose software radios  
Ultrawideband satellite receivers  
Instrumentation  
Radars  
Signals intelligence (SIGINT)  
FUNCTIONAL BLOCK DIAGRAM  
AVDD2  
(1.8V)  
AVDD3  
(2.5V)  
AVDD1 AVDD1_SR  
DVDD  
DRVDD  
DRVDD2  
(1.8V)  
SPIVDD  
(1.8V)  
(0.975V)  
(0.975V)  
(0.975V) (0.975V)  
BUFFER  
DIGITAL DOWN  
CONVERTER  
(DDC)  
14  
VIN+A  
ADC  
CORE  
VIN–A  
VCM_AB  
FD_A  
2
JESD204B  
HIGH-SPEED  
SERIALIZER  
SERDOUT0AB±  
SERDOUT1AB±  
Tx  
OUTPUTS  
FAST  
DETECT  
SIGNAL  
MONITOR  
FD_B  
BUFFER  
DIGITAL DOWN  
CONVERTER  
(DDC)  
14  
VIN+B  
VIN–B  
ADC  
CORE  
SIGNAL  
MONITOR  
AND FAST  
DETECT  
SYSREF±  
JESD204B  
SUBCLASS 1  
CONTROL  
CLOCK  
GENERATION  
CLK+  
CLK–  
SYNCINB±AB  
SYNCINB±CD  
÷2  
÷4  
÷8  
BUFFER  
DIGITAL DOWN  
CONVERTER  
(DDC)  
14  
VIN+C  
ADC  
CORE  
VIN–C  
2
VCM_CD  
JESD204B  
HIGH-SPEED  
SERIALIZER  
SERDOUT0CD±  
SERDOUT1CD±  
Tx  
FD_C  
FAST  
DETECT  
SIGNAL  
MONITOR  
OUTPUTS  
FD_D  
BUFFER  
DIGITAL DOWN  
CONVERTER  
(DDC)  
14  
VIN+D  
VIN–D  
ADC  
CORE  
SPI CONTROL  
PDWN/STBY  
AD9694  
DRGND  
AGND  
SDIO  
SCLK CSB  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2016 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
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