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AD9697

更新时间: 2024-11-05 14:57:23
品牌 Logo 应用领域
亚德诺 - ADI 转换器模数转换器
页数 文件大小 规格书
130页 2162K
描述
14 位 1300 MSPS JESD204B 模数转换器

AD9697 数据手册

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14-Bit, 1300 MSPS, JESD204B,  
Analog-to-Digital Converter  
AD9697  
Data Sheet  
FEATURES  
APPLICATIONS  
JESD204B (Subclass 1) coded serial digital outputs  
Communications  
Lane rates up to 16 Gbps  
Diversity multiband, multimode digital receivers  
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE  
General-purpose software radios  
Ultrawideband satellite receiver  
Instrumentation  
Total power dissipation: 1.00 W at 1300 MSPS  
SNR: 65.6 dBFS at 172.3 MHz (1.59 V p-p analog input full scale)  
SFDR: 78 dBFS at 172.3 MHz (1.59 V p-p analog input full scale)  
Noise density  
−153.9 dBFS/Hz (1.59 V p-p analog input full scale)  
−155.6 dBFS/Hz (2.04 V p-p analog input full scale)  
0.95 V, 1.8 V, and 2.5 V supply operation  
No missing codes  
Oscilloscopes  
Spectrum analyzers  
Network analyzers  
Integrated RF test solutions  
Internal ADC voltage reference  
Radars  
Flexible differential input voltage range  
1.36 V p-p to 2.04 V p-p (1.59 V p-p typical)  
2 GHz usable analog input full power bandwidth  
Amplitude detect bits for efficient AGC implementation  
4 integrated digital downconverters  
48-bit NCO  
Electronic support measures, electronic counter measures,  
and electronic counter to counter measures  
High speed data acquisition systems  
DOCSIS 3.0 CMTS upstream receive paths  
Hybrid fiber coaxial digital reverse path receivers  
Wideband digital predistortion  
Programmable decimation rates  
Differential clock input  
SPI control  
Integer clock divide by 2 and divide by 4  
Flexible JESD204B lane configurations  
On-chip dithering to improve small signal linearity  
FUNCTIONAL BLOCK DIAGRAM  
AVDD1  
(0.95V)  
AVDD2  
(1.8V)  
AVDD3 AVDD1_SR  
(2.5V) (0.95V)  
DVDD  
DRVDD1 DRVDD2 SPIVDD  
(0.95V)  
(0.95V)  
(1.8V)  
(1.8V)  
SIGNAL  
MONITOR  
SERDOUT0±  
SERDOUT1±  
SERDOUT2±  
SERDOUT3±  
JESD204B  
4
DIGITAL DOWN-  
CONVERTER  
LINK  
AND  
FAST  
DETECT  
Tx  
OUTPUTS  
14  
VIN+  
VIN–  
ADC  
CORE  
BUFFER  
VREF  
SYNCINB±  
PDWN/STBY  
JESD204B  
SUBCLASS 1  
CONTROL  
CLOCK  
DISTRIBUTION  
SYSREF±  
CLK+  
FD/GPIO1  
GPIO2  
GPIO MUX  
SPI AND  
CONTROL  
REGISTERS  
CLK–  
÷2  
÷4  
AD9697  
AGND  
SDIO SCLK CSB  
DRGND  
DGND  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2018 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 

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