Datasheet > AD9695BCPZRL7-1300

AD9695BCPZRL7-1300

更新时间： 2024-11-04 19:44:43

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
136页	3341K
描述
14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter

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14-Bit, 1300 MSPS/625 MSPS, JESD204B,

Dual Analog-to-Digital Converter

Data Sheet

AD9695

FEATURES

APPLICATIONS

Communications

JESD204B (Subclass 1) coded serial digital outputs

Lane rates up to 16 Gbps

1.6 W total power at 1300 MSPS

800 mW per ADC channel

SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range)

SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range)

Noise density

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, WCDMA, GSM, LTE

General-purpose software radios

Ultrawideband satellite receiver

Instrumentation

Oscilloscopes

−153.9 dBFS/Hz (1.59 V p-p input range)

−155.6 dBFS/Hz (2.04 V p-p input range)

0.95 V, 1.8 V, and 2.5 V supply operation

No missing codes

Spectrum analyzers

Network analyzers

Integrated RF test solutions

Radars

Internal ADC voltage reference

Flexible input range

Electronic support measures, electronic counter measures,

and electronic counter-counter measures

High speed data acquisition systems

DOCSIS 3.0 CMTS upstream receive paths

Hybrid fiber coaxial digital reverse path receivers

Wideband digital predistortion

1.36 V p-p to 2.04 V p-p (1.59 V p-p typical)

2 GHz usable analog input full power bandwidth

>95 dB channel isolation/crosstalk

Amplitude detect bits for efficient AGC implementation

2 integrated digital downconverters per ADC channel

48-bit NCO

Programmable decimation rates

Differential clock input

SPI control

Integer clock divide by 2 and divide by 4

Flexible JESD204B lane configurations

On-chip dithering to improve small signal linerarity

FUNCTIONAL BLOCK DIAGRAM

DRVDD1 DRVDD2 SPIVDD

AVDD1

(0.95V)

AVDD2

(1.8V)

AVDD3 AVDD1_SR

DVDD

(0.95V)

(2.5V)

(0.95V)

(1.8V)

BUFFER

VIN+A

VIN–A

ADC

CORE

DIGITAL DOWN-

CONVERTER

JESD204B

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

LINK

AND

FAST

DETECT

SIGNAL

MONITOR

DIGITAL DOWN-

CONVERTER

OUTPUTS

VIN+B

VIN–B

ADC

CORE

BUFFER

VREF

SYNCINB±

PDWN/STBY

JESD204B

SUBCLASS 1

CONTROL

CLOCK

DISTRIBUTION

SYSREF±

CLK+

FD_A/GPIO_A0

FD_B/GPIO_B0

GPIO MUX

SPI AND

CONTROL

REGISTERS

CLK–

÷2

÷4

AD9695

AGND

SDIO SCLK CSB

DRGND

DGND

Figure 1.

Rev. A

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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