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AD7467BRM PDF预览

AD7467BRM

更新时间: 2024-09-15 22:22:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
15页 167K
描述
1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23

AD7467BRM 数据手册

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pecifications  
1.8V, Micro-Power,  
a
Preliminary Technical Data  
8/10/12-BitADCsin6LeadSOT-23  
AD7466/AD7467/AD7468  
FEATURES  
F U NC T IO NAL B LO C K D IAG RAM  
Specified for VDD of 1.8 V to 3.6 V  
Low Pow er:  
V
DD  
0.9 m W m ax at 60 kSPS w ith 3.6 V Supplies  
0.4 m W m ax at 100 kSPS w ith 1.8 V Supplies  
Fast Throughput Rate: 100 kSPS  
12/10/8-BIT  
Wide Input Bandw idth:  
V
T/H  
SUCCESSIVE  
APPROXIMATION  
ADC  
IN  
70dB SNR at 30 kHz Input Frequency  
Flexible Pow er/ Serial Clock Speed Managem ent  
No Pipeline Delays  
High Speed Serial Interface  
SPI/ QSPI/ µWire/ DSP Com patible  
SCLK  
Standby Mode: 0.5 µA m ax  
6-Lead SOT-23 Package and 8 lead µSOIC  
CONTROL LOGIC  
SDATA  
CS  
AD7466/67/68  
APPLICATIONS  
Battery Pow ered System s  
Medical Instrum ents  
Ram ote Data Acquisition  
Isolated Data Acquisition  
GND  
P R O D U C T H IG H LIG H T S  
1. Specified for Supply voltages of 1.8 V to 3.6 V  
G E NE R AL D E S C R IP T IO N  
T he AD 7466/AD 7467/AD 7468 are 12/10/8-bit, high  
speed, low power, successive-approximation ADCs re-  
spectively. T he parts operate from a single 1.8 V to 3.6 V  
power supply and feature throughput rates up to 100  
kSPS. T he parts contain a low-noise, wide bandwidth  
track/hold amplifier which can handle input frequencies in  
excess of 100 kHz.  
2. 8/10/12-Bit ADCs in a SOT -23 package.  
3. H igh T hroughput with Low Power Consumption  
4 . Flexible Power/Serial Clock Speed Management  
The conversion rate is determined by the serial clock  
allowing the conversion time to be reduced through the  
serial clock speed increase. Automatic power down after  
conversion, which allows the average power cunsumption  
to be reduced when in powerdown. Power consumption  
is 0.5 µA max when in powerdown.  
T he conversion process and data acquisition are controlled  
using CS and the serial clock, allowing the devices to  
interface with microprocessors or DSPs. T he input signal  
is sampled on the falling edge of CS and the conversion is  
also initiated at this point. T here are no pipelined delays  
associated with the part.  
5. Reference derived from the power supply.  
6. N o Pipeline D elay  
T he part features a standard successive-approximation  
ADC with accurate control of the conversions via a CS  
input.  
T he AD7466/AD7467/AD7468 use advanced design tech-  
niques to achieve very low power dissipation at high  
throughput rates.  
T he reference for the part is taken internally from VDD.  
T his allows the widest dynamic input range to the ADC.  
T hus the analog input range for the part is 0 to VDD. T he  
conversion rate is determined by the SCLK.  
REV. PrC 07/01  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 781/ 329-4700  
Fax: 781/ 326-8703  
World Wide Web Site: http:/ / w w w.analog.com  
Analog Devices, Inc., 2001  

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