pecifications
1.8V, Micro-Power,
a
Preliminary Technical Data
8/10/12-BitADCsin6LeadSOT-23
AD7466/AD7467/AD7468
FEATURES
F U NC T IO NAL B LO C K D IAG RAM
Specified for VDD of 1.8 V to 3.6 V
Low Pow er:
V
DD
0.9 m W m ax at 60 kSPS w ith 3.6 V Supplies
0.4 m W m ax at 100 kSPS w ith 1.8 V Supplies
Fast Throughput Rate: 100 kSPS
12/10/8-BIT
Wide Input Bandw idth:
V
T/H
SUCCESSIVE
APPROXIMATION
ADC
IN
70dB SNR at 30 kHz Input Frequency
Flexible Pow er/ Serial Clock Speed Managem ent
No Pipeline Delays
High Speed Serial Interface
SPI/ QSPI/ µWire/ DSP Com patible
SCLK
Standby Mode: 0.5 µA m ax
6-Lead SOT-23 Package and 8 lead µSOIC
CONTROL LOGIC
SDATA
CS
AD7466/67/68
APPLICATIONS
Battery Pow ered System s
Medical Instrum ents
Ram ote Data Acquisition
Isolated Data Acquisition
GND
P R O D U C T H IG H LIG H T S
1. Specified for Supply voltages of 1.8 V to 3.6 V
G E NE R AL D E S C R IP T IO N
T he AD 7466/AD 7467/AD 7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs re-
spectively. T he parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. T he parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.
2. 8/10/12-Bit ADCs in a SOT -23 package.
3. H igh T hroughput with Low Power Consumption
4 . Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5 µA max when in powerdown.
T he conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. T he input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. T here are no pipelined delays
associated with the part.
5. Reference derived from the power supply.
6. N o Pipeline D elay
T he part features a standard successive-approximation
ADC with accurate control of the conversions via a CS
input.
T he AD7466/AD7467/AD7468 use advanced design tech-
niques to achieve very low power dissipation at high
throughput rates.
T he reference for the part is taken internally from VDD.
T his allows the widest dynamic input range to the ADC.
T hus the analog input range for the part is 0 to VDD. T he
conversion rate is determined by the SCLK.
REV. PrC 07/01
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Analog Devices, Inc., 2001