1.6 V, Micropower
12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7466/AD7467/AD7468*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Specified for VDD of 1.6 V to 3.6 V
Low Power:
V
DD
0.62 mW Typ at 100 kSPS with 3 V Supplies
0.48 mW Typ at 50 kSPS with 3.6 V Supplies
0.12 mW Typ at 100 kSPS with 1.6 V Supplies
Fast Throughput Rate: 200 kSPS
Wide Input Bandwidth:
12-/10-/8-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
V
IN
71 dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
SCLK
SDATA
CS
CONTROL
LOGIC
High Speed Serial Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Automatic Power Down
AD7466/AD7467/AD7468
Power-Down Mode: 8 nA Typ
6-Lead SOT-23 Package
GND
8-Lead MSOP Package
APPLICATIONS
Battery-Powered Systems
Medical Instruments
Remote Data Acquisition
Isolated Data Acquisition
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7466/AD7467/AD7468 are 12-/10-/8-bit, high speed,
low power, successive approximation ADCs, respectively.
The parts operate from a single 1.6 V to 3.6 V power supply
and feature throughput rates up to 200 kSPS. The parts con-
tain a low noise, wide bandwidth track-and-hold amplifier that
can handle input frequencies in excess of 3 MHz.
1. Specified for supply voltages of 1.6 V to 3.6 V.
2. 12-/10-/8-Bit ADCs in a SOT-23 package.
3. High throughput rate with low power consumption. Power
consumption in normal mode of operation at 100 kSPS and
3 V is 0.9 mW max.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
4. Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. Automatic power-down after conversion
allows the average power consumption to be reduced when
in power-down. Current consumption is 0.1 µA max and 8 nA
typically when in power-down.
The AD7466/AD7467/AD7468 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
5. Reference derived from the power supply.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to VDD. The conversion
rate is determined by the SCLK.
6. No pipeline delay. The part features a standard successive
approximation ADC with accurate control of the conversions
via a CS input.
*Patent pending
REV. 0
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