Datasheet > AD5323BRUZ-REEL7

AD5323BRUZ-REEL7

更新时间： 2024-09-17 14:28:19

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管转换器
页数	文件大小	规格书
28页	488K
描述
2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 12-Bit DAC

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AD5323BRUZ-REEL7 数据手册

AD5303/AD5313/AD5323

AC CHARACTERISTICS¹

V_DD= 2.5 V to 5.5 V; R_L= 2 kΩ to GND; C_L= 200 pF to GND; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

A, B Version³

Parameter²

Unit

Conditions/Comments

Min

Typ

Max

Output Voltage Settling Time

V_REF= V_DD= 5 V

AD5303

AD5313

AD5323

ꢀ

μs

¼ scale to ¾ scale change (0x40 to 0xc0)

¼ scale to ¾ scale change (0x100 to 0x300)

¼ scale to ¾ scale change (0x400 to 0xc00)

Slew Rate

Major-Code Transition Glitch Energy

0.7

V/μs

nV-s

1 LSB change around major carry

(011 . . . 11 to 100 . . . 00)

Digital Feedthrough

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

0.10

0.01

200

−70

nV-s

kHz

V_REF= 2 V 0.1 V p-p, unbuffered mode

V_REF= 2.5 V 0.1 V p-p, frequency = 10 kHz

¹Guaranteed by design and characterization, not production tested.

²See the Terminology section.

³Temperature range for Version A and Version B: −40°C to +105°C.

TIMING CHARACTERISTICS

V_DD= 2.5 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Limit at T_MIN,T_MAX

Parameter^{1, 2, 3}

Unit

Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK rising edge setup time

Data setup time

(A, B Version)

t₁

t₂

t₃

t₄

t₅

t_ꢀ

t₇

t₈

t₉

t₁₀

t₁₁

ns min

ns max

ns min

4.5

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

LDAC pulse width

100

SCLK falling edge to LDAC rising edge

CLR pulse width

4, 5

t₁₂

SCLK falling edge to SDO invalid

SCLK falling edge to SDO valid

SCLK falling edge to SYNC rising edge

SYNC rising edge to SCLK rising edge

4, 5

t₁₃

t₁₄

t₁₅

¹Guaranteed by design and characterization, not production tested.

²All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 4 and Figure 5.

⁴These are measured with the load circuit of Figure 4.

⁵Daisy-chain mode only (see Figure 47).

Rev. B | Page ꢀ of 28

1...3 4 567 8 9...28

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AD5323BRUZ-REEL7 替代型号

型号	品牌	替代类型	描述	数据表
AD5323BRU-REEL7	ADI	完全替代	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail Vo
AD5323BRUZ	ADI	类似代替	暂无描述
AD5323BRU	ADI	类似代替	+2.5 V to +5.5 V, 230 uA, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs

与AD5323BRUZ-REEL7相关器件

型号	品牌	获取价格	描述	数据表
AD5323BRUZ-REEL71	ADI	获取价格	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail Vo
AD5324	ADI	获取价格	2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC
AD5324ACPZ-REEL7	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5324ACPZ-WP	ADI	获取价格	IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, DSO10, LEAD FREE, 3 X 3 MM, LFCSP
AD5324ARM	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5324ARM-REEL7	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5324ARMZ	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5324ARMZ-REEL7	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5324BCPZ-REEL7	ADI	获取价格	2.5 V to 5.5 V, 500 Î¼A, Quad Voltage Output
AD5324BCPZ-WP	ADI	获取价格	IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, DSO10, LEAD FREE, 3 X 3 MM, LFCSP

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