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AD5324BCPZ-WP

更新时间: 2024-11-08 03:08:59
品牌 Logo 应用领域
亚德诺 - ADI 输入元件转换器
页数 文件大小 规格书
16页 301K
描述
IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, DSO10, LEAD FREE, 3 X 3 MM, LFCSP-10, Digital to Analog Converter

AD5324BCPZ-WP 数据手册

 浏览型号AD5324BCPZ-WP的Datasheet PDF文件第2页浏览型号AD5324BCPZ-WP的Datasheet PDF文件第3页浏览型号AD5324BCPZ-WP的Datasheet PDF文件第4页浏览型号AD5324BCPZ-WP的Datasheet PDF文件第5页浏览型号AD5324BCPZ-WP的Datasheet PDF文件第6页浏览型号AD5324BCPZ-WP的Datasheet PDF文件第7页 
2.5 V to 5.5 V, 500 A, Quad Voltage Output  
8-/10-/12-Bit DACs in 10-Lead LFCSP  
AD5304/AD5314/AD5324*  
FEATURES  
GENERAL DESCRIPTION  
AD5304: 4 Buffered 8-Bit DACs in 10-Lead MSOP and  
10-Lead LFCSP  
A Version: ؎1 LSB INL, B Version: ؎0.625 LSB INL  
AD5314: 4 Buffered 10-Bit DACs in 10-Lead MSOP and  
10-Lead LFCSP  
A Version: ؎4 LSB INL, B Version: ؎2.5 LSB INL  
AD5324: 4 Buffered 12-Bit DACs in 10-Lead MSOP and  
10-Lead LFCSP  
The AD5304/AD5314/AD5324 are quad 8-, 10-, and 12-bit  
buffered voltage output DACs in 10-lead MSOP and 10-lead  
LFCSP packages that operate from a single 2.5 V to 5.5 V sup-  
ply, consuming 500 µA at 3 V. Their on-chip output amplifiers  
allow rail-to-rail output swing to be achieved with a slew rate of  
0.7 V/µs. A 3-wire serial interface is used, which operates at  
clock rates up to 30 MHz and is compatible with standard  
SPI, QSPI, MICROWIRE, and DSP interface standards.  
A Version: ؎16 LSB INL, B Version: ؎10 LSB INL  
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V  
2.5 V to 5.5 V Power Supply  
Guaranteed Monotonic by Design over All Codes  
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V  
Double-Buffered Input Logic  
The references for the four DACs are derived from one reference  
pin. The outputs of all DACs may be updated simultaneously  
using the software LDAC function. The parts incorporate a  
power-on reset circuit, which ensures that the DAC outputs  
power up to 0 V and remain there until a valid write takes place  
to the device. The parts contain a power-down feature that  
reduces the current consumption of the device to 200 nA @  
5 V (80 nA @ 3 V).  
Output Range: 0 V to VREF  
Power-On Reset to 0 V  
Simultaneous Update of Outputs (LDAC Function)  
Low Power, SPI®, QSPI™, MICROWIRE™, and  
DSP Compatible 3-Wire Serial Interface  
On-Chip Rail-to-Rail Output Buffer Amplifiers  
Temperature Range –40؇C to +105؇C  
The low power consumption of these parts in normal operation  
makes them ideally suited to portable battery-operated equip-  
ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,  
reducing to 1 µW in power-down mode.  
APPLICATIONS  
Portable Battery-Powered Instruments  
Digital Gain and Offset Adjustment  
Programmable Voltage and Current Sources  
Programmable Attenuators  
Industrial Process Control  
FUNCTIONAL BLOCK DIAGRAM  
V
REFIN  
DD  
LDAC  
DAC  
INPUT  
STRING  
DAC A  
BUFFER  
BUFFER  
V
V
A
B
OUT  
REGISTER  
REGISTER  
DAC  
REGISTER  
INPUT  
REGISTER  
SCLK  
STRING  
DAC B  
OUT  
INTERFACE  
LOGIC  
SYNC  
DAC  
INPUT  
STRING  
DAC C  
BUFFER  
BUFFER  
V
C
D
OUT  
OUT  
REGISTER  
REGISTER  
DIN  
DAC  
REGISTER  
INPUT  
REGISTER  
STRING  
DAC D  
V
POWER-DOWN  
LOGIC  
POWER-ON  
RESET  
AD5304/AD5314/AD5324  
GND  
*Protected by U.S. Patent No. 5,969,657; other patents pending.  
REV. E  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/461-3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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