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ACS8509T PDF预览

ACS8509T

更新时间: 2024-10-28 06:36:03
品牌 Logo 应用领域
商升特 - SEMTECH ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
68页 703K
描述
Synchronous Equipment Timing Source for SONET or SDH Network Elements

ACS8509T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP100,.63SQ,20针数:100
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.42应用程序:SONET;SDH
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm湿度敏感等级:3
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3,3.3/5 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:ATM/SONET/SDH ICs
最大压摆率:0.222 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

ACS8509T 数据手册

 浏览型号ACS8509T的Datasheet PDF文件第6页浏览型号ACS8509T的Datasheet PDF文件第7页浏览型号ACS8509T的Datasheet PDF文件第8页浏览型号ACS8509T的Datasheet PDF文件第10页浏览型号ACS8509T的Datasheet PDF文件第11页浏览型号ACS8509T的Datasheet PDF文件第12页 
ACS8509 SETS  
ADVANCED COMMUNICATIONS  
FINAL  
DATASHEET  
The minimum being 0 and the maximum 65535, gives a frequency being 77.76 MHz. The actual spot frequencies  
-700 ppm to +500 ppm adjustment range of the output  
frequencies.  
supported are:  
• 2 kHz,  
For example, if the crystal was oscillating at 12.8 MHz  
+ 5 ppm, then the calibration value in the register to give  
a -5 ppm adjustment in output frequencies to  
• 4 kHz,  
• 8 kHz (and N x 8 kHz),  
• 1.544 MHz (SONET)/2.048 MHz (SDH),  
• 6.48 MHz,  
compensate for the crystal inaccuracy, would be:  
39321 - (5 / 0.02) = 39071 (decimal)  
• 19.44 MHz,  
Input Interfaces  
• 25.92 MHz,  
The ACS8509 supports up to four input reference clock  
sources from input types TIN1, TIN2 and TIN3 using TTL/  
CMOS I/O technologies. These interface technologies  
support +3.3 V and +5 V operation.  
• 38.88 MHz,  
• 51.84 MHz,  
• 77.76 MHz.  
Over-Voltage Protection  
The frequency selection is programmed via the  
cnfg_ref_source_frequency register. The internal DPLL  
will normally lock to the selected input at the frequency of  
the input, e.g. 19.44 MHz will lock the DPLL phase  
comparisons at 19.44 MHz. It is, however, possible to  
utilize an internal pre-divider to the DPLL to divide the  
input frequency before it is used for phase comparisons in  
the DPLL. This pre-divider can be used in one of 2 ways:  
The ACS8509 may require Over-Voltage Protection on  
input reference clock ports according to ITU  
Recommendation K.41. Semtech protection devices are  
recommended for this purpose (see separate Semtech  
data book).  
Input Reference Clock Ports  
1. Any of the supported spot frequencies can be divided  
to 8 kHz by setting the lock8K bit (bit 6) in the  
appropriate cnfg_ref_source_frequency register  
location. For good jitter tolerance for all frequencies  
and for operation at 19.44 MHz and above, use  
lock8K. It is possible to choose which edge of the  
8 kHz input to lock to, by setting the appropriate bit of  
the cnfg_control1 register.  
Table 6 gives details of the input reference ports, showing  
the input technologies and the range of frequencies  
supported on each port; the default spot frequencies and  
default priorities assigned to each port on power-up or by  
reset are also shown. Note that SDH and SONET networks  
use different default frequencies; the network type is pin-  
selectable using the SONSDHB pin). Specific frequencies  
and priorities are set by configuration.  
2. Any multiple of 8 kHz between 1544 kHz to 100 MHz  
can be supported by using the DivN feature (bit 7 of  
the cnfg_ref_source_frequency register). Any  
reference input can be set to use DivN independently  
of the frequencies and configurations of the other  
inputs.  
Although each input port is shown as belonging to one of  
the types, TIN1, TIN2 or TIN3, they are fully interchangeable  
as long as the selected speed is within the maximum  
operating speed of the input port technology.  
SDH and SONET networks use different default  
frequencies; the network type is selectable using the  
config_mode register 34 Hex, bit 2.  
Any reference input with the DivN bit set in the  
cnfg_ref_source_frequency register will employ the  
internal pre-divider prior to the DPLL locking.  
For SONET, config_mode register 34 Hex, bit 2 = 1, for  
SDH config_mode register 34 Hex, bit 2 = 0. On power-up  
or by reset, the default will be set by the state of the  
SONSDHB pin (pin 100). Specific frequencies and  
priorities are set by configuration.  
The cnfg_freq_divn register contains the divider ratio N  
where the reference input will get divided by (N+1) where  
0<N<214-1. The cnfg_ref_source_frequency register  
must be set to the closest supported spot frequency to the  
input frequency, but must be lower than the input  
frequency. When using the DivN feature the post-divider  
TTL ports (compatible also with CMOS signals) support  
clock speeds up to 100 MHz, with the highest spot  
Revision 2.00/January 2006 © Semtech Corp.  
Page9  
www.semtech.com  

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