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ACS8510 PDF预览

ACS8510

更新时间: 2024-10-27 22:38:59
品牌 Logo 应用领域
商升特 - SEMTECH ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
69页 743K
描述
Synchronous Equipment Timing Source for SONET or SDH Network Elements

ACS8510 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Not Recommended零件包装代码:QFP
包装说明:LFQFP, QFP100,.63SQ,20针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.39应用程序:SONET;SDH
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm功能数量:1
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3,3.3/5 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:ATM/SONET/SDH ICs最大压摆率:0.2 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

ACS8510 数据手册

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ACS8510 SETS  
Synchronous Equipment Timing Source  
for SONET or SDH Network Elements  
FINAL  
ADVANCED COMMUNCIATIONS  
Description  
Features  
The ACS8510 is a highly integrated, single-chip •Suitable for Stratum 3E*, 3, 4E and 4 SONET  
solution for the Synchronous Equipment Timing or SDH Equipment Clock (SEC) applications  
Source (SETS) function in a SONET or SDH Net- •Meets AT&T, ITU-T, ETSI and Telcordia specifi-  
work Element. The device generates SONET or cations  
SDH Equipment Clocks (SEC) and frame synchro- •Accepts 14 individual input reference clocks  
nization clocks. The ACS8510 is fully compliant •Generates 11 output clocks  
with the required specifications and standards.  
•Supports Free-Run, Locked and Holdover  
modes of operation  
The device supports Free-Run, Locked and •Robust input clock source quality monitoring on  
Holdover modes. It also supports all three types all inputs  
of reference clock source: recovered line clock, •Automatic “hit-less” source switchover on loss  
PDH network, and node synchronization. The of input  
ACS8510 generates independent SEC and BITS •Phase build-out for output clock phase conti-  
clocks, an 8 kHz Frame Synchronization clock  
and a 2 kHz Multi-Frame Synchronization clock.  
nuity during input switchover and mode transi-  
tions  
•Microprocessor interface - Intel, Motorola,  
Serial, Multiplexed, EEPROM  
Two ACS8510 devices can be used together in a  
Master/Slave configuration mode allowing sys- •Programmable wander and jitter tracking/  
tem protection against a single ACS8510 failure.  
attenuation 0.1 Hz to 20 Hz  
•Support for Master/Slave device configuration  
alignment and hot/standby redundancy  
A microprocessor port is incorporated, providing  
access to the configuration and status registers •IEEE 1149.1 JTAG Boundary Scan  
for device setup and monitoring. The ACS8510 •Single 3.3 v operation. 5 v I/O compatible  
supports IEEE 1149.1 JTAG boundary scan.  
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.  
Block Diagram  
•Operating temperature (ambient) -40°C to  
+85°C  
•Available in 100 pin LQFP package  
Input  
Output  
Ports  
11 Output Ports  
14 Input  
Ports  
includin g:  
Reference  
Dig ital  
Loop  
Filter  
1.544/2.048 M Hz  
3.088/4.096 M Hz  
6.176/8.182 M Hz  
12.352/16.384 M Hz  
6.48 MHz  
19.44 MHz  
25.92 MHz  
38.88 MHz  
51.84 MHz  
77.76 MHz  
155.52 MHz  
311.04 MHz  
AM I 64/8 kHz  
2 kHz MFrSync  
8 kHz FrSync  
Source  
TOUT4  
selector  
Divider  
PFD  
DTO  
including:  
AM I 64/8 kHz  
2 kHz  
2xTOUT4  
DPLL/F req. Synthesis  
8 kHz  
6xTIN1  
4xTIN2  
4xTIN3  
N x 8 kHz  
1.544 MHz  
2.048 MHz  
6.48 MHz  
19.44 MHz  
25.92 MHz  
38.88 MHz  
51.84 MHz  
77.76 MHz  
155.52 MHz  
Monitors  
7xTOUT0  
Dig ital  
Loop  
Filter  
PFD  
DTO  
APLL  
TOUT0  
selector  
Div ider  
Frequency  
Dividers  
MFrSync  
FrSync  
MFrSync  
DPLL/Freq. Synthesis  
T CK  
TDI  
IEEE  
1149.1  
JTAG  
Priority  
Table  
Register  
Set  
Chip Clock  
Generator  
Microprocessor  
Port  
TMS  
T RST  
TDO  
TCXO (*OCXO)  
CLK  
Revision 2.07/Jan 2001 ã2001 Semtech Corp  
www.semtech.com  

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