ACS8510 Rev2.1 SETS
Synchronous Equipment Timing Source
for SONET or SDH Network Elements
FINAL
ADVANCED COMMUNICATIONS
Description
Features
The ACS8510 is a highly integrated, single-chip •Suitable for Stratum 3E*, 3, 4E and 4 SONET
solution for the Synchronous Equipment Timing or SDH Equipment Clock (SEC) applications
Source (SETS) function in a SONET or SDH Net- •Meets AT&T, ITU-T, ETSI and Telcordia
work Element. The device generates SONET or specifications
SDH Equipment Clocks (SEC) and frame synchro- •Accepts 14 individual input reference clocks
nization clocks. The ACS8510 is fully compliant •Generates 11 output clocks
with the required specifications and standards.
•Supports Free-run, Locked and Holdover
modes of operation
•Robust input clock source quality monitoring on
all inputs
•Automatic ‘hit-less’ source switchover on loss
of input
•Phase build out for output clock phase
continuity during input switchover and mode
transitions
The device supports Free-run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
•Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EPROM
•Programmable wander and jitter tracking
attenuation 0.1 Hz to 20 Hz
•Support for Master/Slave device configuration
alignment and hot/standby redundancy
•IEEE 1149.1 JTAG Boundary Scan
•Single +3.3 V operation, +5 V I/O compatible
•Operating temperature (ambient) -40°C to
+85°C
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
Rev2.1 adds choice of edge alignment for 8kHz
input, as well as a low jitter n x E1/DS1 output
mode. Other minor changes are made, with all
described in Appendix A.
•Available in 100 pin LQFP package
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
Block Diagram
Figure 1. Simple Block Diagram
2 x AMI
10 x TTL
Input
Output
2 x PECL/LVDS
1 x AMI
Programmable;
Ports
Ports
6 x TTL
Digital
64/8kHz
2kHz
2 x PECL/LVDS
TOUT4
Divider
PFD
Loop
Filter
DTO
Programmable:
64/8kHz
4kHz
selector
N x 8kHz
1.544/2.048MHz
3.088/4.096MHz
6.176/8.182MHz
12.352/16.384MHz
6.48MHz
1.544/2.048MHz
6.48MHz
DPLL/Freq. Synthesis
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
14xSEC
9xSEC
Monitors
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
Digital
155.52MHz
311.04MHz
PFD
Loop
Filter
DTO
APLL
TOUT0
selector
Divider
Frequency
Dividers
2kHz MFrSync
8kHz FrSync
FrSync
MFrSync
DPLL/Freq. Synthesis
MFrSync
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Register
Set
Chip Clock
Generator
Priority
Table
Microprocessor
Port
TCXO (*OCXO)
Revision 2.00/September 2003 Semtech Corp.
www.semtech.com
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