Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> ACS8509T

ACS8509T

更新时间： 2024-02-04 01:42:53

品牌	Logo	应用领域
商升特 - SEMTECH		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式
页数	文件大小	规格书
68页	703K
描述
Synchronous Equipment Timing Source for SONET or SDH Network Elements

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技术参数
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ACS8509T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP, QFP100,.63SQ,20	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.42	应用程序：	SONET;SDH
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e3
长度：	14 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP100,.63SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3,3.3/5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	ATM/SONET/SDH ICs
最大压摆率：	0.222 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

ACS8509T 数据手册

ACS8509 SETS

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Table 6 Input Reference Source Selection and Priority Table

Port Number

Channel

Number (Bin)

Port Type

Input Port

Technology

Frequencies Supported

Default

Priority

SEC1

0111

1000

1011

T_IN1

TTL/CMOS

Up to 100 MHz (see Note (i))

Default (SONET): 19.44 MHz

Default (SDH): 19.44 MHz

SEC2

SEC3

T_IN1

TTL/CMOS

Up to 100 MHz (see Note (i))

Default (SONET): 19.44 MHz

Default (SDH): 19.44 MHz

T_IN2

Up to 100 MHz (see Note (i))

12/1 (Note

(ii))

Default (Master) (SONET): 1.544 MHz

Default (Master) (SDH): 2.048 MHz

Default (Slave) 6.48 MHz

SEC4

1101

T_IN2

TTL/CMOS

Up to 100 MHz (see Note (i))

Default (SONET): 1.544 MHz

Default (SDH): 2.048 MHz

Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being

77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz,

19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH is selected using the SONSDHB pin. When the

SONSDHB pin is High SONET is selected, when the SONSDHB pin is Low SDH is selected.

(ii) Input port SEC4 is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or PORB). The default setup

of Master or Slave SEC4 priority is determined by the MSTSLVB pin.

frequency must be 8 kHz, which is indicated by setting the To lock to 10.000 MHz:

lock8k bit high (bit 6 in cnfg_ref_source_frequency

1. The cnfg_ref_source_frequency register is set to

11XX0010 (binary) to set the DivN, lock8k bits, and

monitors disabled (If the frequency monitors are disabled,

the frequency to 6.48 MHz. (XX = “leaky bucket” ID for

they are disabled for all inputs regardless of the input

this input).

configurations, in this case only activity monitoring will

2. The frequency monitors are disabled in cnfg_monitors

take place). Whilst any number of inputs can be set to use

the DivN feature, only one N can be programmed, hence

all inputs using the DivN feature must require the same

division to get to 8 kHz.

3. The DivN register is set to 4E1 Hex (1249 decimal).

Input Wander and Jitter Tolerance

DivN Examples

The ACS8509 is compliant to the requirements of all

relevant standards, principally ITU Recommendation

G.825^[15], ANSI T1.101-1999^[1]and ETSI ETS 300 462-5

(1996)^[4].

To lock to 2.000 MHz:

1. The cnfg_ref_source_frequency register is set to

11XX0001 (binary) to set the DivN, lock8k bits, and

the frequency to E1/DS1. (XX = “leaky bucket” ID for

this input).

All reference clock inputs have a tight frequency tolerance

but a generous jitter tolerance. Pullin, hold-in and pull-out

ranges are specified for each input port in Table 7.

Minimum jitter tolerance masks are specified in Figures 3

and 4, and Tables 8 and 9, respectively. The ACS8509 will

tolerate wander and jitter components greater than those

shown in Figure 3 and Figure 4, up to a limit determined

by a combination of the apparent long-term frequency

offset caused by wander and the eye-closure caused by

jitter (the input source will be rejected if the offset pushes

2. The cnfg_mode register (34Hex) bit 2 needs to be set

to 1 to select SONET frequencies (DS1).

3. The frequency monitors are disabled in cnfg_monitors

4. The DivN register is set to F9 Hex (249 decimal).

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与ACS8509T相关器件

型号	品牌	获取价格	描述	数据表
ACS8510	SEMTECH	获取价格	Synchronous Equipment Timing Source for SONET or SDH Network Elements
ACS8510_03	SEMTECH	获取价格	Synchronous Equipment Timing Source for SONET or SDH Network Elements
ACS8510REV2.1	SEMTECH	获取价格	Synchronous Equipment Timing Source for SONET or SDH Network Elements
ACS8510REV2.1SETS	ETC	获取价格	Synchronous Equipment Timing Source for SONET or SDH Network Elements
ACS8510REV2.1T	SEMTECH	获取价格	Support Circuit,
ACS8510T	SEMTECH	获取价格	暂无描述
ACS8512	SEMTECH	获取价格	ATM/SONET/SDH IC, PQFP64
ACS8514	SEMTECH	获取价格	Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Inpu
ACS8514T	SEMTECH	获取价格	Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Inpu
ACS8515	SEMTECH	获取价格	Line Card Protection Switch for SONET or SDH Network Elements

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