5秒后页面跳转
A43E16321G-95F PDF预览

A43E16321G-95F

更新时间: 2024-01-31 17:48:55
品牌 Logo 应用领域
联笙电子 - AMICC 时钟动态存储器内存集成电路
页数 文件大小 规格书
45页 724K
描述
Synchronous DRAM, 2MX32, 7ns, CMOS, PBGA90, CSP-90

A43E16321G-95F 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:LFBGA, BGA90,9X15,32Reach Compliance Code:unknown
风险等级:5.75访问模式:FOUR BANK PAGE BURST
最长访问时间:7 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):105 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PBGA-B90
长度:13 mm内存密度:67108864 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
功能数量:1端口数量:1
端子数量:90字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA90,9X15,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH电源:1.8 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.4 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.00001 A
子类别:DRAMs最大压摆率:0.1 mA
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:8 mm
Base Number Matches:1

A43E16321G-95F 数据手册

 浏览型号A43E16321G-95F的Datasheet PDF文件第7页浏览型号A43E16321G-95F的Datasheet PDF文件第8页浏览型号A43E16321G-95F的Datasheet PDF文件第9页浏览型号A43E16321G-95F的Datasheet PDF文件第11页浏览型号A43E16321G-95F的Datasheet PDF文件第12页浏览型号A43E16321G-95F的Datasheet PDF文件第13页 
A43E16321  
Mode Register Filed Table to Program Modes  
Register Programmed with MRS  
Address  
BA1  
BA0  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Function  
0
0
RFU W.B.L  
TM  
CAS Latency  
BT  
Burst Length  
(Note 3)  
(Note 1)  
(Note 2)  
Test Mode  
Type  
CAS Latency  
Burst Type  
Burst Length  
A8 A7  
A6 A5 A4  
Latency  
A3  
Type  
A2 A1 A0  
BT=0  
BT=1  
0
0
1
0
1
0
Mode Register Set  
0
0
0
0
0
1
0
1
0
Reserved  
0
1
Sequential  
Interleave  
0
0
0
0
0
1
0
1
0
1
2
4
1
2
4
Vendor  
Use  
-
2
Only  
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
3
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
8
8
Reserved  
Reserved  
Reserved  
Reserved  
Reserved Reserved  
Reserved Reserved  
Reserved Reserved  
256(Full) Reserved  
Write Burst Length  
Length  
A9  
0
Burst  
1
Single Bit  
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.  
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.  
3. BA1=0, BA0=0 select the Mode Register (vs. the Extended Mode Register).  
Extended Mode Register Table  
BA1  
BA0  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Address Bus (Ax)  
1
0
Bank  
DS  
PASR  
All have to be set to “0”  
0
Up/Down  
(Note)  
Driver Strength  
Driver Strength  
Partial-Array Self Refresh  
A6  
0
A5  
0
Driver Strength  
A7  
A2  
A1  
0
A0  
0
Self Refresh Coverage  
Four Banks  
Full  
3/4  
1/2  
1/4  
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1
Two Banks (Bank 0 & 1)  
One Bank (Bank 0)  
RFU  
1
0
1
0
1
1
1
1
X
0
X
0
RFU  
1
Four Banks  
0
1
Two Banks (Bank 2 & 3)  
One Bank (Bank 2)  
RFU  
1
0
1
1
X
X
RFU  
Note: BA1=1, BA0=0 select the Extended Mode Register (vs. the Mode Register)  
PRELIMINARY (February, 2008, Version 0.1)  
9
AMIC Technology, Corp.  

与A43E16321G-95F相关器件

型号 品牌 获取价格 描述 数据表
A43E16321G-95UF AMICC

获取价格

Synchronous DRAM, 2MX32, 7ns, CMOS, PBGA90, CSP-90
A43E1632G-75I AMICC

获取价格

1M X 16 Bit X 4 Banks Synchronous DRAM
A43E1632G-95I AMICC

获取价格

1M X 16 Bit X 4 Banks Synchronous DRAM
A43E1632V-75I AMICC

获取价格

1M X 16 Bit X 4 Banks Synchronous DRAM
A43E1632V-95I AMICC

获取价格

1M X 16 Bit X 4 Banks Synchronous DRAM
A43E26161 AMICC

获取价格

1M X 16 BIT X 4 BANKS LOW POWER SYNCHRONOUS DRAM
A43E26161AG-75F AMICC

获取价格

DRAM
A43E26161AG-75UF AMICC

获取价格

DRAM
A43E26161AG-95F AMICC

获取价格

DRAM
A43E26161AG-95UF AMICC

获取价格

DRAM