v1.0
®
Automotive ProASIC3 Flash Family FPGAs
Low Power
Features and Benefits
• 1.5 V Core Voltage
• Support for 1.5-V-Only Systems
High-Temperature AEC-Q100–Qualified Devices
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• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Grade 2 105°C T (115°C T )
A
A
J
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• Grade 1 125°C T (135°C T )
• PPAP Documentation
Firm-Error Immune
A•dvAarnchciteedctuI/reOSupports Ultra-High Utilization
• Only Automotive FPGAs to Offer Firm-Error Immunity
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• 700 Mbps DDR, LVDS-Capable I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• 60 k to 1 M System Gates
• Up to 144 kbits of SRAM
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Automotive Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and A3P1000)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
On-Chip User Nonvolatile Memory
• IEEE 1149.1 (JTAG) Boundary Scan Test
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®
• Pin-Compatible Packages across the Automotive ProASIC 3
Family
• 350 MHz System Performance
Clock Conditioning Circuit (CCC) and PLL
• 3.3 V, 66 MHz 64-Bit PCI
• Six CCC Blocks, One with an Integrated PLL
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 350 MHz)
®
• FlashLock to Secure FPGA Contents (anti-tampering)
SRAMs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
Automotive ProASIC3 Product Family
ProASIC3 Devices
System Gates
A3P060
60 k
1,536
18
A3P125
125 k
3,072
36
A3P250
250 k
6,144
36
A3P1000
1 M
24,576
144
32
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
4
8
8
FlashROM Bits
1 k
Yes
1
1 k
1 k
1 k
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals*
I/O Banks
Yes
1
Yes
1
Yes
1
18
18
18
18
2
2
4
4
Maximum User I/Os
96
133
157
300
Package Pins
VQFP
VQ100
FG144
VQ100
FG144
VQ100
FG144, FG256
FBGA
FG144, FG256, FG484
Note: *Six chip-wide (main) globals and three additional global networks in each quadrant are available.
January 2008
I
© 2008 Actel Corporation