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A3P060-1VQG100I PDF预览

A3P060-1VQG100I

更新时间： 2024-09-16 18:27:07
品牌 Logo 应用领域
ACTEL 时钟栅可编程逻辑
页数 文件大小 规格书
144页 4877K
描述
Field Programmable Gate Array, 60000 Gates, CMOS, PQFP100, 0.50 MM PITCH, GREEN, VQFP-100

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A3P060-1VQG100I 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：0.50 MM PITCH, GREEN, VQFP-100Reach Compliance Code：unknown
风险等级：5.75JESD-30 代码：S-PQFP-G100
长度：14 mm等效关口数量：60000
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °C组织：60000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压：1.575 V
最小供电电压：1.425 V标称供电电压：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

A3P060-1VQG100I 数据手册

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Revision 1  
®
Automotive ProASIC3 Flash Family FPGAs  
Low Power  
Features and Benefits  
High-Temperature AEC-Q100–Qualified Devices  
•
•
•
1.5 V Core Voltage  
Support for 1.5-V-Only Systems  
Low-Impedance Flash Switches  
•
•
•
Grade 2 105°C T (115°C T )  
A J  
High-Performance Routing Hierarchy  
Grade 1 125°C T (135°C T )  
A
J
•
•
•
Segmented, Hierarchical Routing and Clock Structure  
High-Performance, Low-Skew Global Network  
Architecture Supports Ultra-High Utilization  
PPAP Documentation  
Firm-Error Immune  
•
•
Only Automotive FPGAs to Offer Firm-Error Immunity  
Can Be Used without Configuration Upset Risk  
Advanced I/O  
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os  
High Capacity  
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 4 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS  
2.5 V / 5.0 V Input  
•
•
•
60 k to 1 M System Gates  
Up to 144 kbits of SRAM  
Up to 300 User I/Os  
Reprogrammable Flash Technology  
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Automotive Process  
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS (A3P250 and A3P1000)  
•
•
•
Live-at-Power-Up (LAPU) Level 0 Support  
Single-Chip Solution  
Retains Programmed Design when Powered Off  
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths  
Hot-Swappable and Cold-Sparing I/Os  
Programmable Output Slew Rate and Drive Strength  
Weak Pull-Up/-Down  
On-Chip User Nonvolatile Memory  
IEEE 1149.1 (JTAG) Boundary Scan Test  
•
1 kbit of FlashROM with Synchronous Interface  
®
Pin-Compatible Packages across the Automotive ProASIC 3  
High Performance  
Family  
•
•
350 MHz System Performance  
3.3 V, 66 MHz 64-Bit PCI  
Clock Conditioning Circuit (CCC) and PLL  
•
•
Six CCC Blocks, One with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,  
and External Feedback  
In-System Programming (ISP) and Security  
•
Secure ISP Using On-Chip 128-Bit Advanced Encryption  
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)  
•
Wide Input Frequency Range (1.5 MHz up to 350 MHz)  
®
•
FlashLock to Secure FPGA Contents (anti-tampering)  
SRAMs  
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
Table 1 • Automotive ProASIC3 Product Family  
ProASIC3 Devices  
System Gates  
A3P060  
60 k  
1,536  
18  
A3P125  
125 k  
3,072  
36  
A3P250  
250 k  
6,144  
36  
A3P1000  
1 M  
24,576  
144  
32  
VersaTiles (D-flip-flops)  
RAM kbits (1,024 bits)  
4,608-Bit Blocks  
4
8
8
FlashROM Bits  
1 k  
Yes  
1
1 k  
1 k  
1 k  
Secure (AES) ISP  
Integrated PLL in CCCs  
VersaNet Globals1  
I/O Banks  
Yes  
1
Yes  
1
Yes  
1
18  
18  
18  
18  
2
2
4
4
Maximum User I/Os  
96  
133  
157  
300  
Package Pins  
VQFP  
VQ100  
FG144  
VQ100  
FG144  
QNG132  
VQ100  
FG144, FG256  
QNG132  
FBGA  
FG144, FG256, FG484  
QFN2  
Notes:  
1. Six chip-wide (main) globals and three additional global networks in each quadrant are available.  
2. QFN packages are available as RoHS compliant only.  
December 2009  
I
© 2010 Actel Corporation  
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与A3P060-1VQG100I相关器件

型号 品牌 获取价格 描述 数据表
A3P060-1VQG100IY MICROSEMI

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A3P060-1VQG100PP MICROSEMI

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 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG100T ACTEL

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 		Field Programmable Gate Array, 1536 CLBs, 60000 Gates, 350MHz, 1536-Cell, CMOS, PQFP100, 0
A3P060-1VQG100Y MICROSEMI

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 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG100YC MICROSEMI

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 		FPGA
A3P060-1VQG100YES MICROSEMI

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 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG100YI MICROSEMI

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 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG100YPP MICROSEMI

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 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG100YT MICROSEMI

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 		FPGA
A3P060-1VQG144 MICROSEMI

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 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

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