Datasheet > A3P060-1VQG100YT

A3P060-1VQG100YT

更新时间： 2024-09-17 04:04:15

品牌	Logo	应用领域
美高森美 - MICROSEMI		可编程逻辑
页数	文件大小	规格书
154页	7732K
描述
FPGA

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技术参数
数据手册

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A3P060-1VQG100YT 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.76	湿度敏感等级：	3
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	Base Number Matches：	1

A3P060-1VQG100YT 数据手册

Revision 5

Automotive ProASIC3 Flash Family FPGAs

Low Power

Features and Benefits

Extended Temperature AEC-Q100–Qualified Devices

•

1.5 V Core Voltage

Support for 1.5-V-Only Systems

Low-Impedance Flash Switches

•

Grade 2: –40°C to 105°C T (115°C T )

A J

High-Performance Routing Hierarchy

Grade 1: –40°C to 125°C T (135°C T )

•

Segmented, Hierarchical Routing and Clock Structure

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

PPAP Documentation

Firm-Error Immune

•

Only Automotive FPGAs to Offer Firm-Error Immunity

Can Be Used without Configuration Upset Risk

Advanced I/O

•

700 Mbps DDR, LVDS-Capable I/Os

High Capacity

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

•

60 k to 1 M System Gates

Up to 144 kbits of SRAM

Up to 300 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Automotive Process

•

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS (A3P250 and A3P1000)

•

Instant On Level 0 Support

•

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold-Sparing I/Os

Single-Chip Solution

Retains Programmed Design when Powered Off

Programmable Output Slew Rate and Drive Strength

Weak Pull-Up/-Down

On-Chip User Nonvolatile Memory

IEEE 1149.1 (JTAG) Boundary Scan Test

•

1 kbit of FlashROM with Synchronous Interface

Pin-Compatible Packages across the Automotive ProASIC 3

High Performance

Family

•

350 MHz System Performance

3.3 V, 66 MHz 64-Bit PCI

Clock Conditioning Circuit (CCC) and PLL

•

Six CCC Blocks, One with an Integrated PLL

Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

In-System Programming (ISP) and Security

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

•

Wide Input Frequency Range (1.5 MHz up to 350 MHz)

•

FlashLock Designed to Provide High-Level Security for FPGA

SRAMs

Contents (anti-tampering)

•

Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

Table 1 • Automotive ProASIC3 Product Family

ProASIC3 Devices

System Gates

A3P060

60 k

1,536

A3P125

125 k

3,072

A3P250

250 k

6,144

A3P1000

1 M

24,576

144

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

1 k

Yes

1 k

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals1

I/O Banks

Yes

Maximum User I/Os

133

157

300

Package Pins

VQFP

VQ100

FG144

VQ100

FG144

QNG132

VQ100

FG144, FG256

QNG132

FBGA

FG144, FG256, FG484

QFN²

Notes:

1. Six chip-wide (main) globals and three additional global networks in each quadrant are available.

2. QFN packages are available as RoHS compliant only.

January 2013

12 3 4 5 6 7...154

中文翻译

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与A3P060-1VQG100YT相关器件

型号	品牌	获取价格	描述	数据表
A3P060-1VQG144	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG144	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
A3P060-1VQG144ES	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
A3P060-1VQG144ES	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG144I	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG144I	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
A3P060-1VQG144PP	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
A3P060-1VQG144PP	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P060-1VQG144T	ACTEL	获取价格	Automotive ProASIC3 Flash Family FPGAs
A3P060-1VQG144Y	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

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