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ADSP-21160M PDF预览

ADSP-21160M

更新时间: 2024-09-16 23:04:19
品牌 Logo 应用领域
亚德诺 - ADI 电脑
页数 文件大小 规格书
53页 695K
描述
DSP Microcomputer

ADSP-21160M 数据手册

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®
SHARC  
a
DSP Microcomputer  
ADSP-21160M  
SUMMARY  
KEY FEATURES  
High-Performance 32-Bit DSP—Applications in Audio,  
Medical, Military, Graphics, Imaging, and  
Communication  
Super Harvard Architecture—Four Independent Buses  
for Dual Data Fetch, Instruction Fetch, and  
Nonintrusive, Zero-Overhead I/O  
Backwards-Compatible—Assembly Source Level  
Compatible with Code for ADSP-2106x DSPs  
Single-Instruction-Multiple-Data (SIMD) Computational  
Architecture—Two 32-Bit IEEE Floating-Point  
Computation Units, Each with a Multiplier, ALU,  
Shifter, and Register File  
80 MHz (12.5 ns) Core Instruction Rate  
Single-Cycle Instruction Execution, Including SIMD  
Operations in Both Computational Units  
480 MFLOPS Peak and 320 MFLOPS Sustained  
Performance (Based on FIR)  
Dual Data Address Generators (DAGs) with Modulo and  
Bit-Reverse Addressing  
Zero-Overhead Looping and Single-Cycle Loop Setup,  
Providing Efficient Program Sequencing  
IEEE 1149.1 JTAG Standard Test Access Port and  
On-Chip Emulation  
400-Ball 27 
؋
 27 mm Metric PBGA Package  
Integrated Peripherals—Integrated I/O Processor,  
4M Bit On-Chip Dual-Ported SRAM, Glueless  
Multiprocessing Features, and Ports (Serial, Link,  
External Bus, and JTAG)  
FUNCTIONAL BLOCK DIAGRAM  
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SHARC is a registered trademark of Analog Devices, Inc.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel:781/329-4700  
Fax:781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2001  

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