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ADSP-21161NYCAZ110 PDF预览

ADSP-21161NYCAZ110

更新时间: 2024-02-08 00:01:49
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亚德诺 - ADI /
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60页 789K
描述
SHARC Processor

ADSP-21161NYCAZ110 数据手册

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SHARC Processor  
ADSP-21161N  
Integrated peripherals—integrated I/O processor, 1M bit on-  
chip dual-ported SRAM, SDRAM controller, glueless multi-  
processing features, and I/O ports (serial, link, external  
bus, SPI, and JTAG)  
ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit  
floating-point formats  
100 MHz/110 MHz core instruction rate  
Single-cycle instruction execution, including SIMD opera-  
tions in both computational units  
Up to 660 MFLOPs peak and 440 MFLOPs sustained  
performance  
SUMMARY  
High performance 32-Bit DSP—applications in audio, medi-  
cal, military, wireless communications, graphics, imaging,  
motor-control, and telephony  
Super Harvard Architecture—four independent buses for  
dual data fetch, instruction fetch, and nonintrusive zero-  
overhead I/O  
Code compatible with all other sharc family DSPs  
Single-instruction multiple-data (SIMD) computational archi-  
tecture—two 32-bit IEEE floating-point computation units,  
each with a multiplier, ALU, shifter, and register file  
Serial ports offer I2S support via 8 programmable and simul-  
taneous receive or transmit pins, which support up to 16  
transmit or 16 receive channels of audio  
225-ball 17 mm 17 mm CSP_BGA package  
DUAL-PORTED SRAM  
CORE PROCESSOR  
INSTRUCTION  
6
JTAG TEST  
AND EMULATION  
TWO INDEPENDENT  
DUAL-PORTED BLOCKS  
CACHE  
32 u 48-BIT  
TIMER  
I/O PORT  
PROCESSOR PORT  
ADDR DATA  
12  
8
GPIO  
FLAGS  
DATA  
DATA  
ADDR  
ADDR  
ADDR  
DATA  
DAG1  
8 u 4 u 32  
DAG2  
8 u 4 u 32  
PROGRAM  
SEQUENCER  
SDRAM  
CONTROLLER  
IOD  
64  
IOA  
18  
EXTERNAL PORT  
32  
32  
24  
32  
ADDR BUS  
MUX  
PM ADDRESS BUS  
DM ADDRESS BUS  
64  
64  
MULTIPROCESSOR  
INTERFACE  
BUS  
CONNECT  
(PX)  
PM DATA BUS  
DM DATA BUS  
DATA BUS  
MUX  
DATA  
REGISTER  
FILE  
(PEY)  
16 u 40-BIT  
DATA  
REGISTER  
FILE  
(PEX)  
16 u 40-BIT  
HOST PORT  
BARREL  
SHIFTER  
BARREL  
SHIFTER  
MULT  
MULT  
5
DMA  
CONTROLLER  
IOP  
REGISTERS  
(MEMORY MAPPED)  
ALU  
ALU  
16  
20  
4
SERIAL PORTS (4)  
CONTROL,  
STATUS, &  
DATA BUFFERS  
LINK PORTS (2)  
SPI PORTS (1)  
S
I/O PROCESSOR  
Figure 1. ADSP-21161N Functional Block Diagram  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. C Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  

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