Datasheet > 微控制器和处理器 > 数字信号处理器> ADSP-21266SKSTZ-1D

ADSP-21266SKSTZ-1D

更新时间： 2024-11-30 05:15:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
44页	548K
描述
Embedded Processor

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数据手册

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SHARC^®

Embedded Processor

ADSP-21266

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Code compatibility—at assembly level, uses the same

instruction set as other SHARC DSPs

Processes high performance audio while enabling low

system costs

Single-instruction multiple-data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating-point computational

units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O—a parallel port, an SPI port, six serial

ports, a digital audio interface (DAI), and JTAG

DAI incorporates two precision clock generators (PCGs), an

input data port (IDP) that includes a parallel data acquisi-

tion port (PDAP), and three programmable timers, all

under software control by the signal routing unit (SRU)

On-chip memory—2M bits on-chip SRAM and a dedicated 4M

bits on-chip mask-programmable ROM

The ADSP-21266 is available with a 150 MHz or a 200 MHz

core instruction rate. For complete ordering information,

see Ordering Guide on Page 44.

Audio decoders and postprocessor algorithms support

nonvolatile memory that can be configured to contain a

combination of PCM 96 kHz, Dolby^®Digital, Dolby Digital

Surround EX^TM, DTS-ES^TMDiscrete 6.1, DTS-ES Matrix 6.1,

DTS^®96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-

PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and

DTS Neo:6^TM

Various multichannel surround-sound decoders are con-

tained in ROM. For configurations of decoder algorithms,

see Table 2 on Page 6.

DUAL PORTED MEMORY

BLOCK 0

DUAL PORTED MEMORY

BLO CK 1

CORE PROCESSOR

INSTRUCTION

SRAM

1M BIT

SRAM

1M BIT

CACHE

TIMER

ROM

48-BIT

2M BIT

DAG1

DAG2

PROGRAM

SEQ UENCER

ADDR

DATA

ADDR

DATA

PM ADDRESS BUS

DM ADDRESS BUS

64 PM DATA BUS

64 DM DATA BUS

IOD

(32)

IOA

(18)

DMA CONTROLLER

PX REGISTER

22 CHANNELS

GPIO FLAGS/

IRQ/TIMEXP

PROCESSING

ELEMENT

(PEX)

PROCESSING

ELEMENT

(PEY)

SPI PORT (1)

ADDRES S/

DATA BUS / GPIO

CONTROL/GPIO

SERIAL PORTS (6)

JTAG TEST & EMULATION

PARALLEL

PORT

IOP

REGISTERS

(MEMORY MAPPED)

SIGNAL

RO UTI NG

UNIT

INPUT

DATA PORTS (8)

PARALLEL DATA

ACQUISITION PORT

CONTROL,

STATUS,

DATA BUFFERS

PRECISION CLOCK

GENERATORS (2)

TIMERS (3)

DIGITAL AUDIO INTERFACE

I/O PROCESSOR

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

FAX: 781.461.3113

www.analog.com

12 3 4 5 6 7...44

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与ADSP-21266SKSTZ-1D相关器件

型号	品牌	获取价格	描述	数据表
ADSP-21266SKSTZ-200X	ADI	获取价格	IC,DSP,32-BIT,CMOS,QFP,144PIN,PLASTIC
ADSP-21266SKSTZ-2B	ADI	获取价格	SHARC Embedded Processor
ADSP-21266SKSTZ-2C	ADI	获取价格	SHARC Embedded Processor
ADSP-21266SKSTZ-2D	ADI	获取价格	SHARC Embedded Processor
ADSP-21267	ADI	获取价格	Preliminary Technical Data
ADSP-21267SKBCZ-X	ADI	获取价格	Preliminary Technical Data
ADSP-21267SKSTZ-X	ADI	获取价格	Preliminary Technical Data
ADSP-21362	ADI	获取价格	SHARC Processor
ADSP-21362BBC-1AA	ADI	获取价格	SHARC Processor
ADSP-21362BBCZ-1AA	ADI	获取价格	SHARC Processor

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