SHARC®
Embedded Processor
ADSP-21266
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
The ADSP-21266 processes high performance audio while
enabling low system costs
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI® port, six serial
ports, a digital audio interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) that includes a parallel data acquisi-
tion port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—2M bits of on-chip SRAM and a dedicated
4M bits of on-chip mask-programmable ROM
The ADSP-21266 is available with a 150 MHz or a 200 MHz
core instruction rate. For complete ordering information,
see Ordering Guide on Page 44.
Audio decoders and post processor algorithms support:
Nonvolatile memory can be configured to contain a combi-
nation of PCM 96 kHz, Dolby® Digital, Dolby Digital
Surround EXTM, DTS-ESTM Discrete 6.1, DTS-ES Matrix 6.1,
DTS® 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-
PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and
DTS Neo:6TM
Various multichannel surround-sound decoders are con-
tained in ROM. For configurations of decoder algorithms,
see Table 2 on Page 6.
DUAL PORTED MEMORY
BLOCK 0
DUAL PORTED MEMORY
BLO CK 1
CORE PROCESSOR
INSTRUCTION
SRAM
1M BIT
SRAM
1M BIT
CACHE
TIMER
ROM
ROM
2M BIT
2M BIT
DAG1
DAG2
PROGRAM
SEQ UENCER
ADDR
DATA
ADDR
DATA
32
32
PM ADDRESS BUS
DM ADDRESS BUS
64
64
PM DATA BUS
DM DATA BUS
IOD
(32)
IOA
(18)
DMA CONTROLLER
PX REGISTER
4
22 CHANNELS
GPIO FLAGS/
IRQ/TIMEXP
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
4
SPI PORT (1)
16
ADDRES S/
DATA BUS / GPIO
3
6
CONTROL/GPIO
SERIAL PORTS (6)
JTAG TEST & EMULATION
PARALLEL
PORT
IOP
REGISTERS
(MEMORY MAPPED)
20
SIGNAL
RO UTI NG
UNIT
INPUT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
CONTROL,
STATUS,
DATA BUFFERS
PRECISION CLOCK
GENERATORS (2)
S
3
TIMERS (3)
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
Figure 1. Functional Block Diagram
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Rev. B
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