SHARC Processors
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SUMMARY
High performance, 32-bit/40-bit, floating-point processor
The ADSP-2136x processors are available with a 333 MHz
core instruction rate and unique peripherals such as the
digital audio interface, S/PDIF transceiver, DTCP (digital
transmission content protection protocol), serial ports,
8-channel asynchronous sample rate converter, precision
clock generators, and more. For complete ordering infor-
mation, see Ordering Guide on Page 53.
optimized for high performance processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM
Code compatible with all other members of the SHARC family
4 BLOCKS OF ON-CHIP MEMORY
CORE PROCESSOR
INSTRUCTION
BLOCK3
BLOCK1
BLOCK2
BLOCK0
SRAM
1M BIT
SRAM
1M BIT
SRAM
0.5M BIT
SRAM
0.5M BIT
CACHE
TIMER
ROM
ROM
32 u 48-BIT
2M BIT
2M BIT
ADDR
DATA
ADDR
ADDR
ADDR
DATA
DATA
DATA
DAG1
8 uꢀ4 u 32
DAG2
8 uꢀ4 u 32
PROGRAM
SEQUENCER
32
PM ADDRESS BUS
DM ADDRESS BUS
32
PM DATA BUS
DM DATA BUS
64
64
IOA
IOA
IOA
SPI
IOA
IOD
IOD
IOD
IOD
PX REGISTER
SPORTS
IDP
PCG
TIMERS
SRC
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
SIGNAL
ROUTING
UNIT
IOP REGISTERS
(MEMORY-MAPPED)
S/PDIF
DTCP
6
JTAGTEST & EMULATION
I/O PROCESSOR
AND PERIPHERALS
S
Figure 1. Functional Block Diagram—Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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