SHARC® Processor
ADSP-21363
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21363 is available with a 333 MHz core instruction
rate. For complete ordering information, see Ordering
Guide on Page 44
a
Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for professional audio processing
At 333 MHz/2 GFLOPs, with unique audio centric peripherals
such as the Digital Audio Interface the ADSP-21363 SHARC
processor is ideal for applications that require industry
leading equalization, reverberation and other effects
processing
Single-Instruction Multiple-Data (SIMD) computational
architecture
Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit
extended precision floating-point computational units,
each with a multiplier, ALU, shifter, and register file
4 BLOCKS OF ON-CHIP MEMORY
CORE PROCESSOR
INSTRUCTION
BLOCK 0
SRAM
1M BIT ROM
2M BIT
BLOCK 1
BLOCK 2
BLOCK 3
SRAM
1M BIT
CACHE
TIMER
SRAM
0.5M BIT
SRAM
0.5M BIT
ROM
2M BIT
32 X 48-BIT
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
32
PM ADDRESS BUS
32
64
DM ADDRESS BUS
PM DATA BUS
64
DM DATA BUS
IOA
IOD
IOA
IOD
IOA
IOD
IOA
IOD
PX REGISTER
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
SPI
SPORTS
IDP
PCG
IOP REGISTERS
(MEMORY MAPPED)
SIGNAL
ROUTING
UNIT
TIMERS
6
JTAG TEST & EMULATION
I/O PROCESSOR
AND PERIPHERALS
SEE “ADSP-21363 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
S
Figure 1. Functional Block Diagram – Processor Core
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Rev. PrA
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