SHARC® Processor
a
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SUMMARY
High performance, 32-bit/40-bit, floating-point processor
optimized for high performance processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM
Code compatible with all other members of the SHARC family
The ADSP-2136x processors are available with a 333 MHz
core instruction rate and unique peripherals such as the digi-
tal audio interface, S/PDIF transceiver, DTCP (digital
transmission content protection protocol), serial ports,
8-channel asynchronous sample rate converter, precision
clock generators, and more. For complete ordering informa-
tion, see Ordering Guide on Page 52.
4 BLOCKS OF ON-CHIP MEMORY
CORE PROCESSOR
INSTRUCTION
BLOCK 0
SRAM
1M BIT ROM
2M BIT
BLOCK 1
BLOCK 2
BLOCK 3
SRAM
1M BIT
CACHE
TIMER
SRAM
0.5M BIT
SRAM
0.5M BIT
ROM
2M BIT
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
DAG1
DAG2
PROGRAM
SEQUENCER
32
PM ADDRESS BUS
32
64
DM ADDRESS BUS
PM DATA BUS
64
DM DATA BUS
IOA
IOD
IOA
IOD
IOA
IOD
IOA
IOD
SPI
SPORTS
IDP
PCG
TIMERS
SRC
PX REGISTER
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
IOP REGISTERS
(MEMORY MAPPED)
SIGNAL
ROUTING
UNIT
SPDIF
DTCP
6
JTAG TEST AND EMULATION
I/O PROCESSOR
AND PERIPHERALS
S
Figure 1. Functional Block Diagram—Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. A
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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