ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Up to 12 TDM stream support, each with 128 channels per
frame
KEY FEATURES—PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-2136x
performs 2 GFLOPS/666 MMACs
3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit
in blocks 2 and 3) for simultaneous access by the core pro-
cessor and DMA
4M bit on-chip ROM (2M bit in block 0 and 2M bit in block 1)
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single-instruction multiple-data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Parallelism in buses and computational units allows single
cycle execution (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the pro-
cessor core, configurable as eight channels of serial data or
seven channels of serial data, and up to a 20-bit wide paral-
lel data channel
Signal routing unit provides configurable and flexible con-
nections between all DAI components–six serial ports, one
SPI port, eight channels of asynchronous sample rate con-
verters, an S/PDIF receiver/transmitter, three timers, an SPI
port,10 interrupts, six flag inputs, six flag outputs, and
20 SRU I/O pins (DAI_Px)
Two serial peripheral interfaces (SPI): primary on dedicated
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI
Full-duplex operation
Master slave mode multimaster support
Open drain outputs
Programmable baud rates, clock polarities, and phases
3 muxed flag/IRQ lines
1 muxed flag/timer expired line
Transfers between memory and core at a sustained
5.4G bytes/s bandwidth at 333 MHz core instruction rate
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter
supports:
INPUT/OUTPUT FEATURES
DMA controller supports:
25 DMA channels for transfers between ADSP-2136x internal
memory and a variety of peripherals
32-bit DMA transfers at peripheral clock speed, in parallel
with full-speed processor execution
Asynchronous parallel port provides access to asynchronous
external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I2S, or right-justified serial data input with
16-, 18-, 20- or 24-bit word widths (transmitter)
Two channel mode and single channel double frequency
(SCDF) mode
Sample rate converter (SRC) contains a serial input port,
de-emphasis filter, sample rate converter (SRC) and serial
output port providing up to –140 dB SNR performance (see
Table 2 on Page 4)
Supports left-justified, I2S, TDM, and right-justified
24-, 20-, 18-, and 16-bit serial formats (input)
Pulse-width modulation provides:
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in nonpaired mode
ROM-based security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
55M byte per sec transfer rate
External memory access in a dedicated DMA channel
8-bit to 32-bit and 16-bit to 32-bit packing options
Programmable data cycle duration: 2 CCLK to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two pre-
cision clock generators, an input data port, three timers, an
S/PDIF transceiver, a DTCP cipher, an 8-channel asynchro-
nous sample rate converter, an SPI port, and a signal
routing unit
Six dual data line serial ports that operate at up to 41.67M
bits/s on each data line—each has a clock, frame sync, and
two data lines that can be configured as either a receiver or
transmitter pair
Left-justified sample pair and I2S support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I2S-compatible stereo devices per
serial port
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA package (see Ordering Guide on
Page 52)
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Rev. A
|
Page 2 of 52
|
December 2006
5秒后页面跳转
一文带你解读74HC244资料手册：特性、应用场景、封装方式、引脚配置说明、电气参数、推荐替代型号
AD623资料手册解读：特性、应用、封装、引脚功能及电气参数
RT9193资料手册解读：RT9193引脚功能、电气参数、替换型号推荐
VIPER22A的资料手册解读、引脚参数说明、代换型号推荐
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
