SHARC® Processor
ADSP-21364
a
Preliminary Technical Data
SUMMARY
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
High performance 32-bit/40-bit floating-point processor
optimized for professional audio processing
Code compatible with all other members of the SHARC family
The ADSP-21364 is available with a 333 MHz core instruction
rate and unique audiocentric peripherals such as the digi-
tal audio interface, S/PDIF transceiver, serial ports, 8-
channel asynchronous sample rate converter, precision
clock generators, and more. For complete ordering infor-
mation, see Ordering Guide on page 53.
At 333 MHz/2 GFLOPs, with unique audio centric peripherals
such as the digital audio interface that includes a high-pre-
cision 8-channel asynchronous sample rate converter
among others, the ADSP-21364 SHARC processor is ideal
for applications that require industry leading equalization,
reverberation and other effects processing
Single-Instruction Multiple-Data (SIMD) computational
architecture
Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit
extended precision floating-point computational units,
each with a multiplier, ALU, shifter, and register file
4 BLOCKS OF ON-CHIP MEMORY
CORE PROCESSOR
INSTRUCTION
BLOCK 0
SRAM
1M BIT ROM
2M BIT
BLOCK 1
BLOCK 2
BLOCK 3
SRAM
1M BIT
CACHE
TIMER
SRAM
0.5M BIT
SRAM
0.5M BIT
ROM
2M BIT
32 X 48-BIT
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
32
PM ADDRESS BUS
32
64
DM ADDRESS BUS
PM DATA BUS
64
DM DATA BUS
IOA
IOD
IOA
IOD
IOA
IOD
IOA
IOD
PX REGISTER
SPI
SPORTS
IDP
PCG
TIMERS
SRC
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
IOP REGISTERS
(MEMORY MAPPED)
SIGNAL
ROUTING
UNIT
SPDIF
6
JTAG TEST & EMULATION
I/O PROCESSOR
AND PERIPHERALS
SEE “ADSP-21364 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
S
Figure 1. Functional Block Diagram—Processor Core
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Rev. PrD
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