SHARC® Processor
ADSP-21267
Preliminary Technical Data
DAI incorporates two precision clock generators (PCG), and
an input data port (IDP) that includes a parallel data acqui-
sition port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—1M Bit of on-chip SRAM and a dedicated
3M Bits of on-chip mask-programmable ROM
The ADSP-21267 is available with a 150 MHz core instruction
rate. For complete ordering information, see Ordering
Guide on page 43
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Code compatible with all other SHARC DSPs
The ADSP-21267 processes high performance audio while
enabling low system costs
Audio decoders and post processor-algorithms support.
Non-volatile memory can be configured to contain a com-
bination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2,
Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES
Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others.
See www.analog.com/SHARC for a complete list
Single-Instruction Multiple-Data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O —a parallel port, an SPI port, four serial
ports, a digital audio interface (DAI) and JTAG test port
Figure 1. FUNCTIONAL BLOCK DIAGRAM
CORE PROCESSOR
DUAL PORTED MEMORY
BLOCK 0
DUAL P ORT ED ME MORY
BLOCK 1
INSTRUCTION
CACHE
32 X 48-BIT
SRAM
0.5 MBIT
SRAM
0.5 MBIT
TIMER
ROM
ROM
1.5 MBIT
1.5 MBIT
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
ADDR
DATA
ADDR
DATA
32
32
PM ADDRESS BUS
DM ADDRESS BUS
64
64
PM DATA BUS
DM DATA BUS
IOD
(32)
IOA
(1 8)
DMA CONTROLLER
22 CHANNELS
PX REGISTER
4
GPIO FLAGS/
IRQ/TIMEXP
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
4
SPI PORT (1)
ADDRE SS/
D ATA BUS/ GP IO
16
3
6
CON TR OL/G PIO
PARALLEL
PORT
SERIAL PORTS (6)
JTAG TEST & EMULATION
IOP
REGISTERS
(MEMORY MAPPED)
SIGNAL
ROUTING
UNIT
INPUT
20
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
CONTROL,
STATUS, &
DAT A BUFFERS
PRECISION CLOCK
GENERATORS (2)
S
3
TI ME RS (3)
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
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Rev. PrA
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